##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

chip northbridge/intel/i945
	# IGD Displays
	register "gfx.ndid" = "3"
	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"

	register "gpu_hotplug" = "0x00000220"
	register "gpu_lvds_use_spread_spectrum_clock" = "1"
	register "gpu_backlight" = "0x1290128"

	device cpu_cluster 0 on
		chip cpu/intel/socket_mFCPGA478
			device lapic 0 on end
		end
	end

	register "pci_mmio_size" = "768"

	device domain 0 on
		device pci 00.0 on # Host bridge
			subsystemid 0x8086 0x7270
		end
		device pci 02.0 on # VGA controller
			subsystemid 0x8086 0x7270
		end
		device pci 02.1 on # display controller
			subsystemid 0x17aa 0x201a
		end
		chip southbridge/intel/i82801gx
			register "pirqa_routing" = "0x0b"
			register "pirqb_routing" = "0x0b"
			register "pirqc_routing" = "0x0b"
			register "pirqd_routing" = "0x0b"
			register "pirqe_routing" = "0x0b"
			register "pirqf_routing" = "0x0b"
			register "pirqg_routing" = "0x0b"
			register "pirqh_routing" = "0x0b"

			# GPI routing
			#  0 No effect (default)
			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
			#  2 SCI (if corresponding GPIO_EN bit is also set)
			register "gpi1_routing" = "2"
			register "gpi7_routing" = "2"

			register "sata_ahci" = "0x1"
			register "sata_ports_implemented" = "0x04"

			register "gpe0_en" = "0x11000006"
			register "alt_gp_smi_en" = "0x1000"

			register "ide_enable_primary" = "1"
			register "ide_enable_secondary" = "1"

			register "c4onc3_enable" = "1"

			register "c3_latency" = "0x23"
			register "p_cnt_throttling_supported" = "1"

			device pci 1b.0 on # Audio Controller
				subsystemid 0x8384 0x7680
			end
			device pci 1c.0 on end # Ethernet
			device pci 1c.1 on end # Atheros WLAN
			device pci 1d.0 on # USB UHCI
				subsystemid 0x8086 0x7270
			end
			device pci 1d.1 on # USB UHCI
				subsystemid 0x8086 0x7270
			end
			device pci 1d.2 on # USB UHCI
				subsystemid 0x8086 0x7270
			end
			device pci 1d.3 on # USB UHCI
				subsystemid 0x8086 0x7270
			end
			device pci 1d.7 on # USB2 EHCI
				subsystemid 0x8086 0x7270
			end
			device pci 1f.0 on # PCI-LPC bridge
				subsystemid 0x8086 0x7270
			end
			device pci 1f.1 on # IDE
				subsystemid 0x8086 0x7270
			end
			device pci 1f.2 on # SATA
				subsystemid 0x8086 0x7270
			end
			device pci 1f.3 on # SMBUS
				subsystemid 0x8086 0x7270
			end
		end
	end
end