#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
chip northbridge/amd/agesa/family14/root_complex
	device cpu_cluster 0 on
			chip cpu/amd/agesa/family14
			  device lapic 0 on end
			end
	end
	device domain 0 on
		subsystemid 0x1022 0x1510 inherit
			chip northbridge/amd/agesa/family14 # CPU side of HT root complex
#					device pci 18.0 on #  northbridge
					chip northbridge/amd/agesa/family14 # PCI side of HT root complex
						device pci 0.0 on end # Root Complex
						device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
						device pci 4.0 on end # PCIE P2P bridge on-board NIC
						device pci 5.0 off end # PCIE P2P bridge
						device pci 6.0 on end # PCIE P2P bridge PCIe slot
						device pci 7.0 off end # PCIE P2P bridge
						device pci 8.0 off end # NB/SB Link P2P bridge
					end # agesa northbridge

					chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
						device pci 11.0 on end # SATA
						device pci 12.0 on end # OHCI USB 0-4
						device pci 12.2 on end # EHCI USB 0-4
						device pci 13.0 on end # OHCI USB 5-9
						device pci 13.2 on end # EHCI USB 5-9
						device pci 14.0 on # SM
						chip drivers/generic/generic #dimm 0-0-0
							device i2c 50 on end
						end
						chip drivers/generic/generic #dimm 0-0-1
							device i2c 51 on end
						end
					end # SM
					device pci 14.1 on end # IDE	0x439c
					device pci 14.2 on end # HDA	0x4383
					device pci 14.3 on # LPC		0x439d
					chip superio/fintek/f81865f
						device pnp 4e.0 off		# Floppy
							io 0x60 = 0x3f0
							irq 0x70 = 6
							drq 0x74 = 2
						end
						device pnp 4e.3 off end			# Parallel Port
						device pnp 4e.4 off end			# Hardware Monitor
						device pnp 4e.5 on #  Keyboard
							io 0x60 = 0x60
							io 0x62 = 0x64
							irq 0x70 = 1
						end
						device pnp 4e.6 off end			# GPIO
						device pnp 4e.a off end			# PME
						device pnp 4e.10 on			# COM1
							io 0x60 = 0x3f8
							irq 0x70 = 4
						end
						device pnp 4e.11 on			# COM2
							io 0x60 = 0x2f8
							irq 0x70 = 3
						end
					end # f81865f
				end #LPC
				device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
				device pci 14.5 off end # OHCI FS/LS USB
				device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
				device pci 15.0 off end # PCIe PortA
				device pci 15.1 off end # PCIe PortB
				device pci 15.2 off end # PCIe PortC
				device pci 15.3 off end # PCIe PortD
				device pci 16.0 off end # OHCI USB 10-13
				device pci 16.2 off end # EHCI USB 10-13
				register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE

				#set up SB800 Fan control registers and IMC fan controls
				register "imc_port_address" = "0x6E"	# 0x2E and 0x6E are common
				register "fan0_enabled" = "1"
				register "fan1_enabled" = "1"
				register "imc_fan_zone0_enabled" = "1"
				register "imc_fan_zone1_enabled" = "1"

				register "fan0_config_vals" = "{ \
					FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
					FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\
					0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
				register "fan1_config_vals" = "{ \
					FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
					FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \
					0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"

				register "imc_zone0_mode1" = " \
					IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
					IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0"
				register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
					IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
				register "imc_zone0_temp_offset" = "0x00"	# No temp offset
				register "imc_zone0_hysteresis" = "0x05"	# Degrees C Hysteresis
				register "imc_zone0_smbus_addr" = "0x98"	# Temp Sensor SMBus address
				register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3"	# SMBUS number
				register "imc_zone0_pwm_step" = "0x01"		# Fan PWM stepping rate
				register "imc_zone0_ramping" = "0x00"		# Disable Fan PWM ramping and stepping

				register "imc_zone1_mode1" = " \
					IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
					IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1"
				register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
					IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
				register "imc_zone1_temp_offset" = "0x00"	# No temp offset
				register "imc_zone1_hysteresis" = "0x05"	# Degrees C Hysteresis
				register "imc_zone1_smbus_addr" = "0x98"	# Temp Sensor SMBus address
				register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3"	# SMBUS number
				register "imc_zone1_pwm_step" = "0x01"		# Fan PWM stepping rate
				register "imc_zone1_ramping" = "0x00"		# Disable Fan PWM ramping and stepping

				# T56N has a Maximum operating temperature  of 90C
				# ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C
				# ZONEX_FANSPEEDS - Fan speeds as a "percentage"
				register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }"
				register "imc_zone0_fanspeeds"  = "{100,  7,  5,  4,  3, 2, 0, 0 }"
				register "imc_zone1_thresholds" = "{ 85, 80, 75, 65,  1, 0, 0, 0, 90 }"
				register "imc_zone1_fanspeeds"  = "{100, 10,  6,  4,  3, 0, 0, 0 }"

			end	#southbridge/amd/cimx/sb800
#			end #  device pci 18.0
# These seem unnecessary
			device pci 18.0 on end
			device pci 18.1 on end
			device pci 18.2 on end
			device pci 18.3 on end
			device pci 18.4 on end
			device pci 18.5 on end
			device pci 18.6 on end
			device pci 18.7 on end

			register "spdAddrLookup" = "
			{
				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
			}"

		end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
	end #domain
end #northbridge/amd/agesa/family14/root_complex