mainboard/intel/galileo: Add vboot support
Add the necessary files and changes to support vboot.
TEST=Build and run on Galileo Gen2 with a SparkFun CryptoShield
1. Obtain and install a SparkFun CryptoShield.
https://www.sparkfun.com/products/13183
2. Edit src/mainboard/intel/galileo/Kconfig to select
VBOOT_WITH_CRYPTO_SHIELD
3. Use make menuconfig to update the config values and select a
payload that will fit. I used SeaBIOS which does not boot.
4. Build coreboot
5. Use the command file below to generate the signed coreboot image.
6. Flash build/coreboot.rom onto the Galileo board
7. The test is successful if verstage detects that it needs recovery
after Phase 1. This is expected because the image does not contain
the GBB section.
8. Flash build/coreboot.signed.bin onto the Galileo board
9. The test is successful if verstage reaches Phase 4 and selects SLOT
A to load the rest of the files.
#!/bin/sh
#
# The necessary tools were built and installed using the following
commands:
#
# pushd 3rdparty/vboot
# make
# sudo make install
# popd
#
# The keys were made using the following command
#
# 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \
# --4k --4k-root --output $PWD/keys
#
#
# Create the GBB area blob
#
gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
#
# Add the empty GBB to the coreboot.rom image
#
dd conv=fdatasync ibs=4096 obs=4096 count=1553 \
if=build/coreboot.rom of=build/coreboot.signed.rom
dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \
of=build/coreboot.signed.rom
dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 \
count=368 if=build/coreboot.rom of=build/coreboot.signed.rom
#
# Add the keys and HWID to the GBB
#
gbb_utility \
--set --hwid='Galileo' \
-r $PWD/keys/recovery_key.vbpubk \
-k $PWD/keys/root_key.vbpubk \
build/coreboot.signed.rom
#
# Sign the firmware with the keys
#
3rdparty/vboot/scripts/image_signing/sign_firmware.sh \
build/coreboot.signed.rom \
$PWD/keys \
build/coreboot.signed.rom
Change-Id: I96170412e7bbc2b9c747ff5e2c845f29220353ed
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18041
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/mainboard/intel/galileo/vboot.fmd b/src/mainboard/intel/galileo/vboot.fmd
new file mode 100644
index 0000000..55e41e5
--- /dev/null
+++ b/src/mainboard/intel/galileo/vboot.fmd
@@ -0,0 +1,52 @@
+#
+# Copyright (C) 2016-2017 Intel Corporation
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but without any warranty; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+FLASH@0xff800000 0x800000 {
+ SI_ALL@0x0 0x200000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x1ff000
+ }
+ SI_BIOS@0x200000 0x600000 {
+ RW_SECTION_A@0x0 0xf0000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0xdffc0
+ RW_FWID_A@0xeffc0 0x40
+ }
+ RW_SECTION_B@0xf0000 0xf0000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0xdffc0
+ RW_FWID_B@0xeffc0 0x40
+ }
+ RW_MRC_CACHE@0x1e0000 0x10000
+ RW_ELOG@0x1f0000 0x4000
+ RW_SHARED@0x1f4000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD@0x1f8000 0x2000
+ RW_NVRAM@0x1fa000 0x6000
+ RW_LEGACY(CBFS)@0x200000 0x200000
+ WP_RO@0x400000 0x200000 {
+ RO_VPD@0x0 0x4000
+ RO_UNUSED@0x4000 0xc000
+ RO_SECTION@0x10000 0x1f0000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0x7f000
+ COREBOOT(CBFS)@0x80000 0x170000
+ }
+ }
+ }
+}