mb/google/myst: Enable chromeOS EC
BUG=b:270624655
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Id18a311097d575973087eb92fd446a5c511f570e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig
index 6537cce..59eabe4 100644
--- a/src/mainboard/google/myst/Kconfig
+++ b/src/mainboard/google/myst/Kconfig
@@ -8,6 +8,8 @@
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_ESPI
select MAINBOARD_HAS_CHROMEOS
select SOC_AMD_PHOENIX
@@ -36,7 +38,8 @@
default "myst" if BOARD_GOOGLE_MYST
config VBOOT
- select VBOOT_NO_BOARD_SUPPORT
+ select EC_GOOGLE_CHROMEEC_SWITCHES
+ select VBOOT_LID_SWITCH
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_STARTS_IN_BOOTBLOCK
diff --git a/src/mainboard/google/myst/Makefile.inc b/src/mainboard/google/myst/Makefile.inc
index 9060a73..418ff9e 100644
--- a/src/mainboard/google/myst/Makefile.inc
+++ b/src/mainboard/google/myst/Makefile.inc
@@ -4,6 +4,7 @@
romstage-y += port_descriptors.c
+ramstage-y += ec.c
ramstage-y += mainboard.c
ramstage-y += port_descriptors.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/myst/chromeos.c b/src/mainboard/google/myst/chromeos.c
index 9f4a3cb..e488e81 100644
--- a/src/mainboard/google/myst/chromeos.c
+++ b/src/mainboard/google/myst/chromeos.c
@@ -1,8 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
+#include <boot/coreboot_tables.h>
#include <vendorcode/google/chromeos/chromeos.h>
+void fill_lb_gpios(struct lb_gpios *gpios) {}
+
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME),
CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME),
diff --git a/src/mainboard/google/myst/dsdt.asl b/src/mainboard/google/myst/dsdt.asl
index 80a9c1f..9c7dc36 100644
--- a/src/mainboard/google/myst/dsdt.asl
+++ b/src/mainboard/google/myst/dsdt.asl
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <variant/ec.h>
DefinitionBlock (
"dsdt.aml",
@@ -13,4 +14,16 @@
{
#include <acpi/dsdt_top.asl>
#include <soc.asl>
+
+ Name (LIDS, 0)
+
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/chromeec/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
+
}
diff --git a/src/mainboard/google/myst/ec.c b/src/mainboard/google/myst/ec.c
new file mode 100644
index 0000000..c369f14
--- /dev/null
+++ b/src/mainboard/google/myst/ec.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <ec/google/chromeec/ec.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void)
+{
+ const struct google_chromeec_event_info info = {
+ .log_events = MAINBOARD_EC_LOG_EVENTS,
+ .sci_events = MAINBOARD_EC_SCI_EVENTS,
+ .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+ .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+ };
+
+ google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c
index 56329ee..bdd4c76 100644
--- a/src/mainboard/google/myst/mainboard.c
+++ b/src/mainboard/google/myst/mainboard.c
@@ -4,6 +4,7 @@
#include <baseboard/variants.h>
#include <console/console.h>
#include <device/device.h>
+#include <variant/ec.h>
static const struct fch_irq_routing fch_irq_map[] = {
{ 0, 0x00, 0x00 },
@@ -30,6 +31,7 @@
static void mainboard_init(void *chip_info)
{
mainboard_configure_gpios();
+ mainboard_ec_init();
}
static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
index 164a47a..ef41b0d 100644
--- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
@@ -1,4 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/phoenix
- device domain 0 on end # domain
+ device domain 0 on
+ device ref lpc_bridge on
+ chip ec/google/chromeec
+ device pnp 0c09.0 alias chrome_ec on end
+ end
+ end
+ end # domain
end # chip soc/amd/phoenix
diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000..c6ab30f
--- /dev/null
+++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_EC_H__
+#define __MAINBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+#include <gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BODY_DETECT_CHANGE))
+
+#define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid, power button or mode change event */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) \
+ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Set GPI for SCI */
+#define EC_SCI_GPI GEVENT_24 /* eSPI system event -> GPE 24 */
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GEVENT_13 /* AGPIO 17 -> GPE 13 */
+
+/* Enable MKBP for buttons and switches */
+#define EC_ENABLE_MKBP_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+#define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
+
+/* Enable EC sync interrupt */
+#define EC_ENABLE_SYNC_IRQ_GPIO
+
+/* EC sync irq */
+#define EC_SYNC_IRQ GPIO_90
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif /* __MAINBOARD_EC_H__ */