tree 18e1d745276c8dfbb59db260cd63846fc4e8f01b
parent c4e68f6080a3ca0f678efce14d778b5602120865
author Shuo Liu <shuo.liu@intel.com> 1709768316 +0800
committer Lean Sheng Tan <sheng.tan@9elements.com> 1710243120 +0000

soc/intel/xeon_sp: Create CXL domains

SPR CXL IIO stack is divided into 2 PCI domains. The 1st domain
is a PCI domain with single bus number and PCIe RCiEPs (Root
Complex Integrated End Points) on it. The 2nd domain is a CXL
domain with remaining buses for CXL 1.0/1.1 end points and
possible SR-IOV (Single Root IO Virtualizaton) VFs (Virtual
Function) if any.

TEST=intel/archercity CRB

P.S. The SUT is not with CXL cards however we hope this refactor
could be integrated first as an improvement of the design.

Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81099
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>