commit a3f7fe8219654aa90ab2ea9458267e5136a03a01
author mtk05962 <bayi.cheng@mediatek.com> Fri Oct 16 13:42:49 2015 +0800
committer Patrick Georgi <pgeorgi@google.com> Sat Mar 12 08:59:20 2016 +0100
tree 7fedcab8b44dfde41513f1e5f6133c4a7eeb9d5f
parent f14f640168ee0269b3c443cd2bba2fc8ee66e419

mt8173: add SPI NOR support

BRANCH=none
BUG=none
TEST=boot oak to kernel on rev1

Change-Id: I0773c81398df445aec16bcfcd0c5a8fe5a588b5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae15c42c2f7d9c2a716e5b6098d85e17279f5eae
Original-Change-Id: I65abf810d35ae5e7156cf6f5730117e690183d18
Original-Signed-off-by: mtk05962 <bayi.cheng@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292693
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13102
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/google/oak/bootblock.c

diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 3d78551..efb489f 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -33,6 +33,34 @@
 	gpio_set_mode(PAD_SCL4, PAD_SCL4_FUNC_SCL4);
 }
 
+static void nor_set_gpio_pinmux(void)
+{
+	/* Set driving strength of EINT4~EINT9 to 8mA
+	 * 0: 2mA
+	 * 1: 4mA
+	 * 2: 8mA
+	 * 3: 16mA
+	 */
+	/* EINT4: 0x10005B20[14:13] */
+	clrsetbits_le16(&mt8173_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
+	/* EINT5~EINT9: 0x10005B30[2:1] */
+	clrsetbits_le16(&mt8173_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
+
+	gpio_set_pull(PAD_EINT4, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+	gpio_set_pull(PAD_EINT5, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+	gpio_set_pull(PAD_EINT6, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+	gpio_set_pull(PAD_EINT7, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+	gpio_set_pull(PAD_EINT8, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+	gpio_set_pull(PAD_EINT9, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+
+	gpio_set_mode(PAD_EINT4, PAD_EINT4_FUNC_SFWP_B);
+	gpio_set_mode(PAD_EINT5, PAD_EINT5_FUNC_SFOUT);
+	gpio_set_mode(PAD_EINT6, PAD_EINT6_FUNC_SFCS0);
+	gpio_set_mode(PAD_EINT7, PAD_EINT7_FUNC_SFHOLD);
+	gpio_set_mode(PAD_EINT8, PAD_EINT8_FUNC_SFIN);
+	gpio_set_mode(PAD_EINT9, PAD_EINT9_FUNC_SFCK);
+}
+
 void bootblock_mainboard_early_init(void)
 {
 	/* Clear UART0 power down signal */
@@ -47,6 +75,9 @@
 	/* set i2c related gpio */
 	i2c_set_gpio_pinmux();
 
+	/* set nor related GPIO */
+	nor_set_gpio_pinmux();
+
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
 
 	setup_chromeos_gpios();