commit a3c6ed0dffe144ca1803b43fe1e0e16a9136793e
author Angel Pons <th3fanbus@gmail.com> Thu Feb 11 13:59:12 2021 +0100
committer Angel Pons <th3fanbus@gmail.com> Fri Feb 12 19:48:34 2021 +0000
tree a8a8bb08065dc46bc3621819cf14414db389e70b
parent 33b59c9170a66a7f6d9c26ccf664714ea81d218d

haswell boards: Correct USB config indentation

Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/slippy/variants/falco/romstage.c

diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c
index de0ac76..8870fae 100644
--- a/src/mainboard/google/slippy/variants/falco/romstage.c
+++ b/src/mainboard/google/slippy/variants/falco/romstage.c
@@ -48,30 +48,30 @@
 	}
 }
 
-	const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
-		/* Length, Enable, OCn#, Location */
-		{ 0x0064, 1, 0,               /* P0: Port A, CN8 */
-		  USB_PORT_BACK_PANEL },
-		{ 0x0052, 1, 0,               /* P1: Port B, CN9  */
-		  USB_PORT_BACK_PANEL },
-		{ 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */
-		  USB_PORT_INTERNAL },
-		{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
-		  USB_PORT_INTERNAL },
-		{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
-		  USB_PORT_INTERNAL },
-		{ 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */
-		  USB_PORT_INTERNAL },
-		{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
-		  USB_PORT_INTERNAL },
-		{ 0x0123, 1, 3,               /* P7: USB2 Port */
-		  USB_PORT_INTERNAL },
-	};
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+	/* Length, Enable, OCn#, Location */
+	{ 0x0064, 1, 0,               /* P0: Port A, CN8 */
+	  USB_PORT_BACK_PANEL },
+	{ 0x0052, 1, 0,               /* P1: Port B, CN9  */
+	  USB_PORT_BACK_PANEL },
+	{ 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */
+	  USB_PORT_INTERNAL },
+	{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
+	  USB_PORT_INTERNAL },
+	{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
+	  USB_PORT_INTERNAL },
+	{ 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */
+	  USB_PORT_INTERNAL },
+	{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
+	  USB_PORT_INTERNAL },
+	{ 0x0123, 1, 3,               /* P7: USB2 Port */
+	  USB_PORT_INTERNAL },
+};
 
-	const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
-		/* Enable, OCn# */
-		{ 1, 0               }, /* P1; Port A, CN8 */
-		{ 1, 0               }, /* P2; Port B, CN9  */
-		{ 0, USB_OC_PIN_SKIP }, /* P3; */
-		{ 0, USB_OC_PIN_SKIP }, /* P4; */
-	};
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+	/* Enable, OCn# */
+	{ 1, 0               }, /* P1; Port A, CN8 */
+	{ 1, 0               }, /* P2; Port B, CN9  */
+	{ 0, USB_OC_PIN_SKIP }, /* P3; */
+	{ 0, USB_OC_PIN_SKIP }, /* P4; */
+};