blob: 155df5878dfaf88d09c5f566c809752d03eba4f4 [file] [log] [blame]
config SOC_INTEL_COMMON_SKYLAKE_BASE
bool
config SOC_INTEL_SKYLAKE
bool
select SOC_INTEL_COMMON_SKYLAKE_BASE
help
Intel Skylake support
config SOC_INTEL_KABYLAKE
bool
select SOC_INTEL_COMMON_SKYLAKE_BASE
help
Intel Kabylake support
if SOC_INTEL_COMMON_SKYLAKE_BASE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_NHLT
select ARCH_ALL_STAGES_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_INTEL_COMMON_HYPERTHREADING
select FSP_M_XIP
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select HAVE_FSP_LOGO_SUPPORT
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select HAVE_INTEL_FSP_REPO
select IOAPIC
select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0
select REG_SCRIPT
select SA_ENABLE_DPR
select PMC_GLOBAL_RESET_ENABLE_LOCK
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
select SOC_INTEL_COMMON_BLOCK_GSPI
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SCS
select SOC_INTEL_COMMON_BLOCK_SGX
select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_THERMAL
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select UDELAY_TSC
select UDK_2015_BINDING
select USE_CAR_NEM_ENHANCED_V1
config FSP_HYPERTHREADING
bool "Enable Hyper-Threading"
default y
config CPU_INTEL_NUM_FIT_ENTRIES
int
default 10
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
config CBFS_SIZE
hex
default 0x200000
config DCACHE_RAM_BASE
hex
default 0xfef00000
config DCACHE_RAM_SIZE
hex
default 0x40000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.
config DCACHE_BSP_STACK_SIZE
hex
default 0x4000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages.
config C_ENV_BOOTBLOCK_SIZE
hex
default 0xC000
config EXCLUDE_NATIVE_SD_INTERFACE
bool
default n
help
If you set this option to n, will not use native SD controller.
config HEAP_SIZE
hex
default 0x80000
config IED_REGION_SIZE
hex
default 0x400000
config PCR_BASE_ADDRESS
hex
default 0xfd000000
help
This option allows you to select MMIO Base Address of sideband bus.
config SMM_RESERVED_SIZE
hex
default 0x200000
config SMM_TSEG_SIZE
hex
default 0x800000
config VGA_BIOS_ID
string
default "8086,0406"
config SKYLAKE_SOC_PCH_H
bool
default n
help
Choose this option if you have a PCH-H chipset.
config NHLT_DMIC_2CH
bool
default n
help
Include DSP firmware settings for 2 channel DMIC array.
config NHLT_DMIC_4CH
bool
default n
help
Include DSP firmware settings for 4 channel DMIC array.
config NHLT_NAU88L25
bool
default n
help
Include DSP firmware settings for nau88l25 headset codec.
config NHLT_MAX98357
bool
default n
help
Include DSP firmware settings for max98357 amplifier.
config NHLT_MAX98373
bool
default n
help
Include DSP firmware settings for max98373 amplifier.
config NHLT_SSM4567
bool
default n
help
Include DSP firmware settings for ssm4567 smart amplifier.
config NHLT_RT5514
bool
default n
help
Include DSP firmware settings for rt5514 DSP.
config NHLT_RT5663
bool
default n
help
Include DSP firmware settings for rt5663 headset codec.
config NHLT_MAX98927
bool
default n
help
Include DSP firmware settings for max98927 amplifier.
config NHLT_DA7219
bool
default n
help
Include DSP firmware settings for DA7219 headset codec.
config FSP_HEADER_PATH
# Use KabylakeFsp for both Skylake and Kabylake as it supports both.
# SkylakeFsp is FSP 1.1 and therefore incompatible.
default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
config FSP_FD_PATH
default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
config MAX_ROOT_PORTS
int
default 24
config NO_FADT_8042
bool
default n
help
Choose this option if you want to disable 8042 Keyboard
config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
int
default 120
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 2
config SOC_INTEL_I2C_DEV_MAX
int
default 6
config CPU_BCLK_MHZ
int
default 100
config CONSOLE_UART_BASE_ADDRESS
hex
default 0xfe030000
depends on INTEL_LPSS_UART_FOR_CONSOLE
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
default 0x30
config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
config IFD_CHIPSET
string
default "sklkbl"
config INTEL_TXT_BIOSACM_ALIGNMENT
hex
default 0x40000 # 256KB
config MAINBOARD_SUPPORTS_SKYLAKE_CPU
bool "Board can contain Skylake CPU"
default y
if SKYLAKE_SOC_PCH_H
config MAINBOARD_SUPPORTS_KABYLAKE_CPU
bool "Board can contain Kaby Lake CPU"
default y if SOC_INTEL_KABYLAKE
endif
if !SKYLAKE_SOC_PCH_H
config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
bool "Board can contain Kaby Lake DUAL core"
default y
config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
bool "Board can contain Kaby Lake QUAD core"
default y
endif
endif