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config SOC_INTEL_CANNONLAKE_BASE
bool
config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
bool
default y if SOC_INTEL_CANNONLAKE_BASE && !SOC_INTEL_CANNONLAKE
help
Single Kconfig option to select common base Cannonlake support.
This Kconfig will help to select majority of CNL SoC features.
Major difference that exist today between
SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS and SOC_INTEL_CANNONLAKE Kconfig
are in FSP Header Files. Hence this Kconfig might help to select
required SoC support FSP headers. Any future Intel SoC would
like to make use of CNL support might just select this Kconfig.
config SOC_INTEL_CANNONLAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select MICROCODE_BLOB_NOT_IN_BLOB_REPO
help
Intel Cannonlake support
config SOC_INTEL_COFFEELAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
help
Intel Coffeelake support
config SOC_INTEL_WHISKEYLAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
help
Intel Whiskeylake support
config SOC_INTEL_COMETLAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
help
Intel Cometlake support
config SOC_INTEL_COMETLAKE_1
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_2
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_S
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_V
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_CANNONLAKE_PCH_H
bool
help
Choose this option if you have a PCH-H chipset.
if SOC_INTEL_CANNONLAKE_BASE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_NHLT
select ARCH_ALL_STAGES_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select FSP_COMPRESS_FSP_S_LZMA
select FSP_M_XIP
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select HAVE_FSP_LOGO_SUPPORT
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC
select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0
select REG_SCRIPT
select PMC_GLOBAL_RESET_ENABLE_LOCK
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SCS
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_THERMAL
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
select FSP_T_XIP if FSP_CAR
select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
config MAX_CPUS
int
default 12
config DCACHE_RAM_BASE
default 0xfef00000
config DCACHE_RAM_SIZE
default 0x40000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.
config DCACHE_BSP_STACK_SIZE
hex
default 0x20400 if FSP_USES_CB_STACK
default 0x4000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be
sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE
hex
depends on FSP_USES_CB_STACK
default 0x10000
help
The amount of anticipated heap usage in CAR by FSP.
Refer to Platform FSP integration guide document to know
the exact FSP requirement for Heap setup.
config IFD_CHIPSET
string
default "cnl"
config IED_REGION_SIZE
hex
default 0x400000
config HEAP_SIZE
hex
default 0x8000
config NHLT_DMIC_1CH_16B
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for 1 channel 16B DMIC array.
config NHLT_DMIC_2CH_16B
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for 2 channel 16B DMIC array.
config NHLT_DMIC_4CH_16B
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for 4 channel 16B DMIC array.
config NHLT_MAX98357
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for headset codec.
config NHLT_MAX98373
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for headset codec.
config NHLT_DA7219
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for headset codec.
config MAX_ROOT_PORTS
int
default 24 if SOC_INTEL_CANNONLAKE_PCH_H
default 16
config MAX_PCIE_CLOCKS
int
default 16 if SOC_INTEL_CANNONLAKE_PCH_H
default 6
config SMM_TSEG_SIZE
hex
default 0x800000
config SMM_RESERVED_SIZE
hex
default 0x200000
config PCR_BASE_ADDRESS
hex
default 0xfd000000
help
This option allows you to select MMIO Base Address of sideband bus.
config CPU_BCLK_MHZ
int
default 100
config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
int
default 120
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 216
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 3
config SOC_INTEL_I2C_DEV_MAX
int
default 4 if SOC_INTEL_CANNONLAKE_PCH_H
default 6
config CONSOLE_UART_BASE_ADDRESS
hex
default 0xfe032000
depends on INTEL_LPSS_UART_FOR_CONSOLE
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
default 0x30
config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
config C_ENV_BOOTBLOCK_SIZE
hex
default 0xC000
config CBFS_SIZE
hex
default 0x200000
config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
bool
default n
help
Select this if the board has a SD_PWR_ENABLE pin connected to a
active high sensing load switch to turn on power to the card reader.
This will enable a workaround in ASL _PS3 and _PS0 methods to force
SD_PWR_ENABLE to stay low in D3.
choice
prompt "Cache-as-ram implementation"
default USE_CANNONLAKE_CAR_NEM_ENHANCED
help
This option allows you to select how cache-as-ram (CAR) is set up.
config USE_CANNONLAKE_CAR_NEM_ENHANCED
bool "Enhanced Non-evict mode"
select SOC_INTEL_COMMON_BLOCK_CAR
select USE_CAR_NEM_ENHANCED_V1
help
A current limitation of NEM (Non-Evict mode) is that code and data
sizes are derived from the requirement to not write out any modified
cache line. With NEM, if there is no physical memory behind the
cached area, the modified data will be lost and NEM results will be
inconsistent. ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.
config USE_CANNONLAKE_FSP_CAR
bool "Use FSP CAR"
select FSP_CAR
help
Use FSP APIs to initialize and tear down the Cache-As-Ram.
endchoice
config FSP_HEADER_PATH
default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Include/" if SOC_INTEL_COMETLAKE_2
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/" if SOC_INTEL_COMETLAKE_S
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Include/" if SOC_INTEL_COMETLAKE_V
default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE
config FSP_FD_PATH
default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Fsp.fd" if SOC_INTEL_COMETLAKE_1
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Fsp.fd" if SOC_INTEL_COMETLAKE_2
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Fsp.fd" if SOC_INTEL_COMETLAKE_S
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Fsp.fd" if SOC_INTEL_COMETLAKE_V
config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT
int "Debug Consent for CNL"
# USB DBC is more common for developers so make this default to 3 if
# SOC_INTEL_DEBUG_CONSENT=y
default 3 if SOC_INTEL_DEBUG_CONSENT
default 0
help
This is to control debug interface on SOC.
Setting non-zero value will allow to use DBC or DCI to debug SOC.
PlatformDebugConsent in FspmUpd.h has the details.
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0xe00
config INTEL_TXT_BIOSACM_ALIGNMENT
hex
default 0x40000 # 256KB
endif