include/console: Align ramstage Boot State Machine postcodes
This patch ensures all boot state machine postcodes are in right
order. Move POST_ENTRY_RAMSTAGE macro definition after
POST_BS_PAYLOAD_BOOT.
Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52893
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index ee74dcb..677cd36 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -182,14 +182,6 @@
#define POST_PRE_HARDWAREMAIN 0x79
/**
- * \brief Entry into coreboot in RAM stage main()
- *
- * This is the first call in hardwaremain.c. If this code is POSTed, then
- * ramstage has successfully loaded and started executing.
- */
-#define POST_ENTRY_RAMSTAGE 0x80
-
-/**
* \brief Load Payload
*
* Boot State Machine: bs_payload_load()
@@ -204,6 +196,14 @@
#define POST_BS_PAYLOAD_BOOT 0x7b
/**
+ * \brief Entry into coreboot in RAM stage main()
+ *
+ * This is the first call in hardwaremain.c. If this code is POSTed, then
+ * ramstage has successfully loaded and started executing.
+ */
+#define POST_ENTRY_RAMSTAGE 0x80
+
+/**
* \brief Before calling FSP Notify before End of Firmware
*
* Going to call into FSP binary for Notify phase