soc/intel/{adl, cmn, mtl}: Refactor MP Init related configs
This patch optimizes CPU MP Init related configs being used within
multiple SoC directory and moving essential configs into common code
to let the SoC user to choose as per the requirement.
TEST=Able to build and boot google/kano and google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I12adcc04e84244656a0d2dcf97607bd036320887
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 27176ec..dd6bb22 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -75,6 +75,7 @@
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select INTEL_GMA_OPREGION_2_1
select INTEL_TXT_LIB
+ select MP_SERVICES_PPI_V2
select MRC_SETTINGS_PROTECT
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_2
@@ -476,31 +477,6 @@
Note: selection of this config would introduce an additional warm reset in
cold-reset scenarios due to function disabling of the UFS controller.
-choice
- prompt "Multiprocessor (MP) Initialization configuration to use"
- default USE_FSP_MP_INIT
-
-config USE_FSP_MP_INIT
- bool "Use FSP MP init"
- select MP_SERVICES_PPI_V2
- help
- Upon selection, coreboot brings APs from reset and the FSP runs feature programming.
-
-config USE_COREBOOT_MP_INIT
- bool "Use coreboot MP init"
- # FSP assumes ownership of the APs (Application Processors)
- # upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD.
- # Hence, select `MP_SERVICES_PPI_V2_NOOP` config to pass a valid
- # pointer to the CpuMpPpi UPD with FSP_UNSUPPORTED type APIs.
- # This will protect APs from getting hijacked by FSP while coreboot
- # decides to set SkipMpInit UPD.
- select MP_SERVICES_PPI_V2_NOOP
- select RELOAD_MICROCODE_PATCH
- help
- Upon selection, coreboot performs MP Init.
-
-endchoice
-
if STITCH_ME_BIN
config CSE_BPDT_VERSION
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index aa8de99..704f910 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -597,7 +597,7 @@
*/
s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
- if (CONFIG(USE_FSP_MP_INIT))
+ if (CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS))
/*
* Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature
* programming.