mb/google/guybrush: select DISABLE_KEYBOARD_RESET_PIN
Now that we have the DISABLE_KEYBOARD_RESET_PIN Kconfig option, select
it and remove the temporary workaround that was implemented in the
mainboard code in commit 39ef89033624a2d14b0c77cdbdf287dd7d7059e1.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I634d11290dad8c93f10979f06243b1bf84737ae2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index 77d2537..9dd264a 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -9,6 +9,7 @@
def_bool y
select AMD_SOC_CONSOLE_UART
select BOARD_ROMSIZE_KB_16384
+ select DISABLE_KEYBOARD_RESET_PIN
select DISABLE_SPI_FLASH_ROM_SHARING
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c
index ffa6822..72ad7a8 100644
--- a/src/mainboard/google/guybrush/mainboard.c
+++ b/src/mainboard/google/guybrush/mainboard.c
@@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <amdblocks/acpimmio.h>
#include <amdblocks/amd_pci_util.h>
#include <baseboard/variants.h>
#include <device/device.h>
#include <soc/acpi.h>
-#include <soc/southbridge.h>
#include <variant/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -90,16 +88,6 @@
{
size_t base_num_gpios, override_num_gpios;
const struct soc_amd_gpio *base_gpios, *override_gpios;
- u32 reg;
-
- /*
- * Disable KBRST feature
- * KBRSTEN is set to 1 on reset and this causes system reset
- * if GPIO 129 is configured as GPO_LOW.
- * */
- reg = pm_read8(PM_RST_CTRL1);
- reg &= ~KBRSTEN;
- pm_write8(PM_RST_CTRL1, reg);
base_gpios = variant_base_gpio_table(&base_num_gpios);
override_gpios = variant_override_gpio_table(&override_num_gpios);