sb/amd/sr5650: Get rid of device_t

Change-Id: If03864d5e32dfc4a2e5e11a96a4df62699ca4392
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c
index b79efc2..563c67d 100644
--- a/src/southbridge/amd/sr5650/ht.c
+++ b/src/southbridge/amd/sr5650/ht.c
@@ -177,8 +177,8 @@
 
 	if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
 		uint32_t reg;
-		device_t amd_ht_cfg_dev;
-		device_t amd_addr_map_dev;
+		struct device *amd_ht_cfg_dev;
+		struct device *amd_addr_map_dev;
 		resource_t res_base;
 		resource_t res_end;
 		uint32_t base;
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index e198b87..9e2bd92 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -46,9 +46,9 @@
 	0			/* GppPwr */
 };
 
-static void ValidatePortEn(device_t nb_dev);
+static void ValidatePortEn(struct device *nb_dev);
 
-static void ValidatePortEn(device_t nb_dev)
+static void ValidatePortEn(struct device *nb_dev)
 {
 }
 
@@ -56,7 +56,7 @@
 * Compliant with CIM_33's PCIEPowerOffGppPorts
 * Power off unused GPP lines
 *****************************************************************/
-static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
+static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 port)
 {
 	printk(BIOS_DEBUG, "PciePowerOffGppPorts() port %d\n", port);
 	u32 reg;
@@ -124,7 +124,7 @@
 
 /**********************************************************************
 **********************************************************************/
-static void switching_gpp1_configurations(device_t nb_dev, device_t sb_dev)
+static void switching_gpp1_configurations(struct device *nb_dev, struct device *sb_dev)
 {
 	u32 reg;
 	struct southbridge_amd_sr5650_config *cfg =
@@ -165,7 +165,7 @@
 
 /**********************************************************************
 **********************************************************************/
-static void switching_gpp2_configurations(device_t nb_dev, device_t sb_dev)
+static void switching_gpp2_configurations(struct device *nb_dev, struct device *sb_dev)
 {
 	u32 reg;
 	struct southbridge_amd_sr5650_config *cfg =
@@ -203,7 +203,7 @@
 	/* Follow the procedure for PCIE-GPP2 common initialization and
 	 * link training sequence. */
 }
-static void switching_gpp3a_configurations(device_t nb_dev, device_t sb_dev)
+static void switching_gpp3a_configurations(struct device *nb_dev, struct device *sb_dev)
 {
 	u32 reg;
 	struct southbridge_amd_sr5650_config *cfg =
@@ -263,7 +263,7 @@
 * The sr5650 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
 * Space to a 256MB range within the first 4GB of addressable memory.
 *****************************************************************/
-void enable_pcie_bar3(device_t nb_dev)
+void enable_pcie_bar3(struct device *nb_dev)
 {
 	printk(BIOS_DEBUG, "%s\n", __func__);
 	set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30);	/* Enables writes to the BAR3 register. */
@@ -279,7 +279,7 @@
 * We should disable bar3 when we want to exit sr5650_enable, because bar3 will be
 * remapped in set_resource later.
 *****************************************************************/
-void disable_pcie_bar3(device_t nb_dev)
+void disable_pcie_bar3(struct device *nb_dev)
 {
 	printk(BIOS_DEBUG, "%s\n", __func__);
 	pci_write_config32(nb_dev, 0x1C, 0);	/* clear BAR3 address */
@@ -290,7 +290,7 @@
 /*
  * GEN2 Software Compliance
  */
-void init_gen2(device_t nb_dev, device_t dev, u8 port)
+void init_gen2(struct device *nb_dev, struct device *dev, u8 port)
 {
 	u32 reg, val;
 
@@ -358,7 +358,7 @@
  * Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP3a Ports
  * PcieLibCplBufferAllocation
  */
-static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev)
+static void gpp3a_cpl_buf_alloc(struct device *nb_dev, struct device *dev)
 {
 	u8 dev_index;
 	u8 *slave_cpl;
@@ -406,7 +406,7 @@
  * Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP1/PCIE-GPP2 Ports
  * PcieLibCplBufferAllocation
  */
-static void gpp12_cpl_buf_alloc(device_t nb_dev, device_t dev)
+static void gpp12_cpl_buf_alloc(struct device *nb_dev, struct device *dev)
 {
 	u8 gpp_cfg;
 	u8 value;
@@ -442,14 +442,14 @@
 /*
  * Enable LCLK clock gating
  */
-static void EnableLclkGating(device_t dev)
+static void EnableLclkGating(struct device *dev)
 {
 	u8 port;
 	u32 reg = 0;
 	u32 mask = 0;
 	u32 value = 0;
-	device_t nb_dev = dev_find_slot(0, 0);
-	device_t clk_f1= dev_find_slot(0, 1);
+	struct device *nb_dev = dev_find_slot(0, 0);
+	struct device *clk_f1= dev_find_slot(0, 1);
 
 	reg = 0xE8;
 	port = dev->path.pci.devfn >> 3;
@@ -502,7 +502,7 @@
 * port:
 *	p2p bridge number, 4-10
 *****************************************/
-void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
+void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port)
 {
 	uint8_t training_ok = 1;
 
@@ -829,7 +829,7 @@
  * Step 21: Register Locking
  * Lock HWInit Register of each pcie core
  */
-static void lock_hwinitreg(device_t nb_dev)
+static void lock_hwinitreg(struct device *nb_dev)
 {
 	/* Step 21: Register Locking, Lock HWInit Register */
 	set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP1, 1 << 0, 1 << 0);
@@ -844,7 +844,7 @@
  */
 void sr56x0_lock_hwinitreg(void)
 {
-	device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 
 	/* Lock HWInit Register */
 	lock_hwinitreg(nb_dev);
@@ -859,7 +859,7 @@
 /*****************************************
 * Compliant with CIM_33's PCIEConfigureGPPCore
 *****************************************/
-void config_gpp_core(device_t nb_dev, device_t sb_dev)
+void config_gpp_core(struct device *nb_dev, struct device *sb_dev)
 {
 	u32 reg;
 
@@ -886,7 +886,7 @@
 /*****************************************
 * Compliant with CIM_33's PCIEMiscClkProg
 *****************************************/
-void pcie_config_misc_clk(device_t nb_dev)
+void pcie_config_misc_clk(struct device *nb_dev)
 {
 	u32 reg;
 	//struct bus pbus; /* fake bus for dev0 fun1 */
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 47de24c..ec78467 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -36,7 +36,7 @@
 extern void set_pcie_reset(void);
 
 struct resource * sr5650_retrieve_cpu_mmio_resource() {
-	device_t domain;
+	struct device *domain;
 	struct resource *res;
 
 	for (domain = all_devices; domain; domain = domain->next) {
@@ -51,7 +51,7 @@
 }
 
 /* extension registers */
-u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
+u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg)
 {
 	/*get BAR3 base address for nbcfg0x1c */
 	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
@@ -62,7 +62,7 @@
 	return *((u32 *) addr);
 }
 
-void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)
+void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg_pos, u32 mask, u32 val)
 {
 	u32 reg_old, reg;
 
@@ -81,42 +81,42 @@
 	}
 }
 
-u32 nbpcie_p_read_index(device_t dev, u32 index)
+u32 nbpcie_p_read_index(struct device *dev, u32 index)
 {
 	return nb_read_index((dev), NBPCIE_INDEX, (index));
 }
 
-void nbpcie_p_write_index(device_t dev, u32 index, u32 data)
+void nbpcie_p_write_index(struct device *dev, u32 index, u32 data)
 {
 	nb_write_index((dev), NBPCIE_INDEX, (index), (data));
 }
 
-u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)
+u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index)
 {
 	return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
 }
 
-void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
+void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data)
 {
 	nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
 }
 
-uint32_t l2cfg_ind_read_index(device_t nb_dev, uint32_t index)
+uint32_t l2cfg_ind_read_index(struct device *nb_dev, uint32_t index)
 {
 	return nb_read_index((nb_dev), L2CFG_INDEX, (index));
 }
 
-void l2cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data)
+void l2cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data)
 {
 	nb_write_index((nb_dev), L2CFG_INDEX | (0x1 << 8), (index), (data));
 }
 
-uint32_t l1cfg_ind_read_index(device_t nb_dev, uint32_t index)
+uint32_t l1cfg_ind_read_index(struct device *nb_dev, uint32_t index)
 {
 	return nb_read_index((nb_dev), L1CFG_INDEX, (index));
 }
 
-void l1cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data)
+void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data)
 {
 	nb_write_index((nb_dev), L1CFG_INDEX | (0x1 << 31), (index), (data));
 }
@@ -130,8 +130,8 @@
 void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
 {
 	/* K8 Function1 is address map */
-	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
-	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 
 	if (in_out) {
 		u32 dword, sblk;
@@ -157,7 +157,7 @@
 	}
 }
 
-void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
+void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port)
 {
 	switch (port) {
 	case 2:		/* GPP1, bit4-5 */
@@ -194,7 +194,7 @@
 *	0: no device is present.
 *	1: device is present and is trained.
 ********************************************************************************************************/
-u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
+u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port)
 {
 	u16 count = 5000;
 	u32 lc_state, reg, current_link_width, lane_mask;
@@ -300,7 +300,7 @@
 /*
  * Set Top Of Memory below and above 4G.
  */
-void sr5650_set_tom(device_t nb_dev)
+void sr5650_set_tom(struct device *nb_dev)
 {
 	msr_t sysmem;
 
@@ -315,12 +315,12 @@
 	htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
 }
 
-u32 get_vid_did(device_t dev)
+u32 get_vid_did(struct device *dev)
 {
 	return pci_read_config32(dev, 0);
 }
 
-void detect_and_enable_iommu(device_t iommu_dev) {
+void detect_and_enable_iommu(struct device *iommu_dev) {
 	uint32_t dword;
 	uint8_t l1_target;
 	unsigned char iommu;
@@ -332,7 +332,7 @@
 	if (iommu) {
 		printk(BIOS_DEBUG, "Initializing IOMMU\n");
 
-		device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+		struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 
 		if (!nb_dev) {
 			printk(BIOS_WARNING, "Unable to find SR5690 device!  IOMMU NOT initialized\n");
@@ -496,7 +496,7 @@
 	}
 }
 
-void sr5650_iommu_read_resources(device_t dev)
+void sr5650_iommu_read_resources(struct device *dev)
 {
 	unsigned char iommu;
 	struct resource *res;
@@ -521,7 +521,7 @@
 	compact_resources(dev);
 }
 
-void sr5650_iommu_set_resources(device_t dev)
+void sr5650_iommu_set_resources(struct device *dev)
 {
 	unsigned char iommu;
 	struct resource *res;
@@ -549,12 +549,12 @@
 	pci_dev_set_resources(dev);
 }
 
-void sr5650_iommu_enable_resources(device_t dev)
+void sr5650_iommu_enable_resources(struct device *dev)
 {
 	detect_and_enable_iommu(dev);
 }
 
-void sr5650_nb_pci_table(device_t nb_dev)
+void sr5650_nb_pci_table(struct device *nb_dev)
 {	/* NBPOR_InitPOR function. */
 	u8 temp8;
 	u16 temp16;
@@ -609,9 +609,9 @@
 * case 0 will be called twice, one is by CPU in hypertransport.c line458,
 * the other is by sr5650.
 ***********************************************/
-void sr5650_enable(device_t dev)
+void sr5650_enable(struct device *dev)
 {
-	device_t nb_dev = 0, sb_dev = 0;
+	struct device *nb_dev = NULL, *sb_dev = NULL;
 	int dev_ind;
 	struct southbridge_amd_sr5650_config *cfg;
 
@@ -823,14 +823,14 @@
 {
 	uint8_t *p;
 
-	device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 	if (!nb_dev) {
 		printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "
 				"device!  IVRS table not generated...\n");
 		return (unsigned long)ivrs;
 	}
 
-	device_t iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2));
+	struct device *iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2));
 	if (!iommu_dev) {
 		printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "
 				"IOMMU device!  IVRS table not generated...\n");
@@ -890,7 +890,7 @@
 	return current;
 }
 
-unsigned long southbridge_write_acpi_tables(device_t device,
+unsigned long southbridge_write_acpi_tables(struct device *device,
 						unsigned long current,
 						struct acpi_rsdp *rsdp)
 {