commit a1ef94e822a0a2d1093e62d13ceb6dbeb19b22a1
author Michael Niewöhner <foss@mniewoehner.de> Sun Sep 01 13:53:09 2019 +0200
committer Patrick Georgi <pgeorgi@google.com> Sun Sep 15 20:56:24 2019 +0000
tree 7defef16f2a0645c7778527b6a9ec13e2fb1b2d8
parent 5ea2e405dad22930db8f5e8dcf1a1fe383284919

soc/intel/skylake: add some FSP SATA params

This adds SATA parameters for SpinUp, HotPlug and TestMode to the
Skylake FSP 2.0 interface.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I7ba67879b78c2cb0fd0b0ce832140b213edd5884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35186
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/skylake/chip_fsp20.c

diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index de86936..d1d7d6f 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -283,6 +283,10 @@
 	       sizeof(params->SataPortsEnable));
 	memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
 	       sizeof(params->SataPortsDevSlp));
+	memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug,
+	       sizeof(params->SataPortsHotPlug));
+	memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp,
+	       sizeof(params->SataPortsSpinUp));
 	memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport,
 	       sizeof(params->PcieRpClkReqSupport));
 	memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
@@ -369,6 +373,7 @@
 	tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
 	tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
 	tconfig->PowerLimit4 = config->PowerLimit4;
+	tconfig->SataTestMode = config->SataTestMode;
 	/*
 	 * To disable HECI, the Psf needs to be left unlocked
 	 * by FSP till end of post sequence. Based on the devicetree