diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig
index 35afb07..9d2a5f2 100644
--- a/src/mainboard/intel/cannonlake_rvp/Kconfig
+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig
@@ -4,6 +4,7 @@
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
 	select SOC_INTEL_CANNONLAKE
+	select HAVE_ACPI_TABLES
 	select GENERIC_SPD_BIN
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/intel/cannonlake_rvp/acpi_tables.c b/src/mainboard/intel/cannonlake_rvp/acpi_tables.c
new file mode 100644
index 0000000..3b44754
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/acpi_tables.c
@@ -0,0 +1 @@
+/* Nothing here */
diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
new file mode 100644
index 0000000..712ea05
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x05,		// DSDT revision: ACPI v5.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// global NVS and variables
+	#include <soc/intel/cannonlake/acpi/globalnvs.asl>
+
+	Scope (\_SB) {
+	}
+
+	#if IS_ENABLED(CONFIG_CHROMEOS)
+	// Chrome OS specific
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+	#endif
+}