tree c9bc3a89521e0e7ece9d0e3cfece3cffcdf47acc
parent 87b7ec2ebb94d3c3c14c2fd6ec34ad80af950767
author Tim Wawrzynczak <twawrzynczak@chromium.org> 1619034770 -0600
committer Tim Wawrzynczak <twawrzynczak@chromium.org> 1620274361 +0000

soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities

Change-Id: I97c00e1985f319ff1db57314723d8405c2a6cbd2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>