commit | a11eca149a0aa4d4adb6ef3091c5c4662e10af66 | [log] [tgz] |
---|---|---|
author | Bill XIE <persmule@hardenedlinux.org> | Sat Aug 28 14:59:04 2021 +0800 |
committer | Felix Held <felix-coreboot@felixheld.de> | Sun Aug 29 16:41:12 2021 +0000 |
tree | 644d5e5d0d24c230bce4848bae070968d3cb134a | |
parent | f3c84024b18239bacef6ed30923fe68ac44c0749 [diff] |
superio/nuvoton/nct6776: Correct the definition of NCT6776_GPIOBASE NCT6776's data sheet does say that the virtual LDN of GPIO base should be 0x308, and most mainboards using it usually correctly config it in devicetree.cb under the path 2e.308, but in nct6776.h it used to be defined as 8 from the beginning (an ancient commit 1e3a22649a9, lately revived in commit f95daa510d6), identical to the LDN of WDT, which eliminates the definition of value 2e.308, and makes related resource allocations unable to take effect. (in log we can find "PNP: 002e.308 missing read_resources" if 2e.308 is enabled and assigned with resources) In this commit, NCT6776_GPIOBASE is set to a value consistent with the data sheet. With this commit, resources under 2e.308 of NCT6776 can be allocated successfully. Change-Id: I604bad7ab34a8f57262fdec508e5952cf8eabf1c Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.