commit a0b199c6b4836d1c8f11c2f87e98a5386b69b50f
author Johnny Lin <johnny_lin@wiwynn.com> Mon Jan 30 20:44:05 2023 +0800
committer Lean Sheng Tan <sheng.tan@9elements.com> Wed Mar 22 12:05:59 2023 +0000
tree 33e4a59d4e5fb7e78c7800859a804aa5cbaace0b
parent d5bd8d54a32143c7d126a406eec1c3bcbf0240f5

soc/intel/xeon_sp/spr: Add soc set_cmos_mrc_cold_boot_flag

This soc utility function can set cmos flag to enforce
FSP MRC training.

Change-Id: I88004cbfdcbe8870726493576dfc31de4b6036a9
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/soc/intel/xeon_sp/spr/include/soc/soc_util.h

diff --git a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h
index c961030..e1ed414 100644
--- a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h
+++ b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h
@@ -9,6 +9,22 @@
 #include <hob_systeminfo.h>
 #include <hob_enhancedwarningloglib.h>
 
+/*
+ * Address of the MRC status byte in CMOS. Should be reserved
+ * in mainboards' cmos.layout and not covered by checksum.
+ */
+#define CMOS_OFFSET_MRC_STATUS 0x47
+
+#if CONFIG(USE_OPTION_TABLE)
+#include "option_table.h"
+#if CMOS_VSTART_mrc_status != CMOS_OFFSET_MRC_STATUS * 8
+#error "CMOS start for CPX-SP MRC status byte is not correct, check your cmos.layout"
+#endif
+#if CMOS_VLEN_mrc_status != 8
+#error "CMOS length for CPX-SP MRC status byte is not correct, check your cmos.layout"
+#endif
+#endif
+
 const struct SystemMemoryMapHob *get_system_memory_map(void);
 const struct SystemMemoryMapElement *get_system_memory_map_elment(uint8_t *num);
 
@@ -28,5 +44,6 @@
 
 uint32_t get_ubox_busno(uint32_t socket, uint8_t offset);
 uint32_t get_socket_ubox_busno(uint32_t socket);
+void set_cmos_mrc_cold_boot_flag(bool cold_boot_required);
 
 #endif /* _SOC_UTIL_H_ */

src/soc/intel/xeon_sp/spr/soc_util.c

diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c
index f8d40e3..94d172c 100644
--- a/src/soc/intel/xeon_sp/spr/soc_util.c
+++ b/src/soc/intel/xeon_sp/spr/soc_util.c
@@ -5,7 +5,6 @@
 #include <device/pci.h>
 #include <hob_cxlnode.h>
 #include <intelblocks/cpulib.h>
-#include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/numa.h>
 #include <soc/pci_devs.h>
@@ -13,6 +12,7 @@
 #include <soc/util.h>
 #include <stdlib.h>
 #include <string.h>
+#include <pc80/mc146818rtc.h>
 
 const EWL_PRIVATE_DATA *get_ewl_hob(void)
 {
@@ -161,3 +161,13 @@
 		wrmsr(MSR_BIOS_DONE, msr);
 	}
 }
+
+void set_cmos_mrc_cold_boot_flag(bool cold_boot_required)
+{
+	uint8_t mrc_status = cmos_read(CMOS_OFFSET_MRC_STATUS);
+	uint8_t new_mrc_status = (mrc_status & 0xfe) | cold_boot_required;
+	printk(BIOS_SPEW, "MRC status: 0x%02x want 0x%02x\n", mrc_status, new_mrc_status);
+	if (new_mrc_status != mrc_status)
+		cmos_write(new_mrc_status, CMOS_OFFSET_MRC_STATUS);
+
+}