tree 593424f7bba43c6b2361f305334c3ac8eac3f6e1
parent b25fa1cf9ee3ea51c4c183d2d7f3d79c0bf8d573
author Shuo Liu <shuo.liu@intel.com> 1714124105 +0800
committer Lean Sheng Tan <sheng.tan@9elements.com> 1714671822 +0000

soc/intel/xeon_sp: Add get_cxl_mode

Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.

Add get_cxl_mode so that SoC codes do not need to get this
configuration from VPD any more.

TEST=Build and boot on intel/archercity CRB with no significant log
differences

Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>