libpayload: add x86 ROM variable MTRR support
On x86, coreboot may allocate a variable range MTRR for enabling caching
of the system ROM. Add the ability to parse this structure and add the
result to the sysinfo structure.
An example usage implementation would be to obtain the variable MTRR
index that covers the ROM from the sysinfo structure. Then one would
disable caching and change the MTRR type from uncacheable to
write-protect and enable caching. The opposite sequence is required
to tearn down the caching.
Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2920
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 38bda55..02c9449 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -217,6 +217,18 @@
uint32_t vboot_handoff_size;
};
+#define CB_TAG_X86_ROM_MTRR 0x0021
+struct cb_x86_rom_mtrr {
+ uint32_t tag;
+ uint32_t size;
+ /* The variable range MTRR index covering the ROM. If one wants to
+ * enable caching the ROM, the variable MTRR needs to be set to
+ * write-protect. To disable the caching after enabling set the
+ * type to uncacheable. */
+ uint32_t index;
+};
+
+
#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
struct cb_cmos_option_table {
u32 tag;