soc/mediatek: a common implementation to register BL31 reset
The implementations of register_reset_to_bl31() are the same for
MedaiTek platforms, so we extract them to soc/common/bl31.c.
BUG=None
TEST=build pass
Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c
index b69403e..c67a581 100644
--- a/src/mainboard/google/cherry/mainboard.c
+++ b/src/mainboard/google/cherry/mainboard.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <bl31.h>
#include <boardid.h>
#include <bootmode.h>
#include <console/console.h>
@@ -10,6 +9,7 @@
#include <edid.h>
#include <framebuffer_info.h>
#include <gpio.h>
+#include <soc/bl31.h>
#include <soc/ddp.h>
#include <soc/dpm.h>
#include <soc/dptx.h>
@@ -23,8 +23,6 @@
#include "gpio.h"
-#include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h>
-
/* GPIO to schematics names */
#define GPIO_AP_EDP_BKLTEN GPIO(DGI_D5)
#define GPIO_BL_PWM_1V8 GPIO(DISP_PWM0)
@@ -57,17 +55,6 @@
}
}
-static void register_reset_to_bl31(void)
-{
- static struct bl_aux_param_gpio param_reset = {
- .h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO },
- .gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH },
- };
-
- param_reset.gpio.index = GPIO_RESET.id;
- register_bl31_aux_param(¶m_reset.h);
-}
-
/* Set up backlight control pins as output pin and power-off by default */
static void configure_panel_backlight(void)
{
@@ -160,7 +147,8 @@
if (spm_init())
printk(BIOS_ERR, "spm init failed, system suspend may not work\n");
- register_reset_to_bl31();
+ if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
+ register_reset_to_bl31(GPIO_RESET.id, true);
}
static void mainboard_enable(struct device *dev)