commit 9f3f9154c9f3dd1e3cfbd2703b681c3e9ddf4dc7
author Patrick Rudolph <siro@das-labor.org> Tue Jan 26 20:02:14 2016 +0100
committer Martin Roth <martinroth@google.com> Wed Mar 02 21:46:49 2016 +0100
tree c473e23fc7dc436629f0ca444ccf113173f632e4
parent 2bdeb7f843c707023ea2bd39e314f8eec51c7add

nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk

Instead of hardcoding the maximum supported DDR frequency to
800Mhz (DDR3-1600), read the fuse bits that encode this information.

Test system:
 * Intel IvyBridge
 * Gigabyte GA-B75M-D3H

Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13487
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/northbridge/intel/sandybridge/raminit.c

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 65282d2..c154b23 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -4089,26 +4089,61 @@
 
 static unsigned int get_mem_min_tck(void)
 {
+	u32 reg32;
+	u8 rev;
 	const struct device *dev;
-	const struct northbridge_intel_sandybridge_config *cfg;
+	const struct northbridge_intel_sandybridge_config *cfg = NULL;
 
 	dev = dev_find_slot(0, HOST_BRIDGE);
-	if (!(dev && dev->chip_info))
-		return DEFAULT_TCK;
-
-	cfg = dev->chip_info;
+	if (dev)
+		cfg = dev->chip_info;
 
 	/* If this is zero, it just means devicetree.cb didn't set it */
-	if (cfg->max_mem_clock_mhz == 0)
-		return DEFAULT_TCK;
+	if (!cfg || cfg->max_mem_clock_mhz == 0) {
+		rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
 
-	if (cfg->max_mem_clock_mhz >= 800)
-		return TCK_800MHZ;
-	else if (cfg->max_mem_clock_mhz >= 666)
-		return TCK_666MHZ;
-	else if (cfg->max_mem_clock_mhz >= 533)
-		return TCK_533MHZ;
-	return TCK_400MHZ;
+		if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
+			/* read Capabilities A Register DMFC bits */
+			reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);
+			reg32 &= 0x7;
+
+			switch (reg32) {
+			case 7: return TCK_533MHZ;
+			case 6: return TCK_666MHZ;
+			case 5: return TCK_800MHZ;
+			/* reserved: */
+			default:
+				break;
+			}
+		} else {
+			/* read Capabilities B Register DMFC bits */
+			reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B);
+			reg32 = (reg32 >> 4) & 0x7;
+
+			switch (reg32) {
+			case 7: return TCK_533MHZ;
+			case 6: return TCK_666MHZ;
+			case 5: return TCK_800MHZ;
+			case 4: return TCK_933MHZ;
+			case 3: return TCK_1066MHZ;
+			case 2: return TCK_1200MHZ;
+			case 1: return TCK_1333MHZ;
+			/* reserved: */
+			default:
+				break;
+			}
+		}
+		return DEFAULT_TCK;
+	} else {
+		if (cfg->max_mem_clock_mhz >= 800)
+			return TCK_800MHZ;
+		else if (cfg->max_mem_clock_mhz >= 666)
+			return TCK_666MHZ;
+		else if (cfg->max_mem_clock_mhz >= 533)
+			return TCK_533MHZ;
+		else
+			return TCK_400MHZ;
+	}
 }
 
 void perform_raminit(int s3resume)