commit 9e6d143a82a852ddfa64f20ceb8695939c1dace1
author Aaron Durbin <adurbin@chromium.org> Wed Jul 13 23:21:41 2016 -0500
committer Aaron Durbin <adurbin@chromium.org> Fri Jul 15 08:32:49 2016 +0200
tree 147ee77b05213ace8941dbebe360df972f026517
parent c159bb0d76af801bca405e729c5f4b97a18a5a1d

soc/intel/broadwell: use common Intel ACPI hardware definitions

Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/broadwell/romstage/power_state.c

diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c
index 38a4109..cfb2418 100644
--- a/src/soc/intel/broadwell/romstage/power_state.c
+++ b/src/soc/intel/broadwell/romstage/power_state.c
@@ -52,17 +52,16 @@
 static int prev_sleep_state(struct chipset_power_state *ps)
 {
 	/* Default to S0. */
-	int prev_sleep_state = SLEEP_STATE_S0;
+	int prev_sleep_state = ACPI_S0;
 
 	if (ps->pm1_sts & WAK_STS) {
-		switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
-#if CONFIG_HAVE_ACPI_RESUME
-		case SLP_TYP_S3:
-			prev_sleep_state = SLEEP_STATE_S3;
+		switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
+		case ACPI_S3:
+			if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+				prev_sleep_state = ACPI_S3;
 			break;
-#endif
-		case SLP_TYP_S5:
-			prev_sleep_state = SLEEP_STATE_S5;
+		case ACPI_S5:
+			prev_sleep_state = ACPI_S5;
 			break;
 		}
 		/* Clear SLP_TYP. */
@@ -70,7 +69,7 @@
 	}
 
 	if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
-		prev_sleep_state = SLEEP_STATE_S5;
+		prev_sleep_state = ACPI_S5;
 
 	return prev_sleep_state;
 }

src/soc/intel/broadwell/romstage/raminit.c

diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 376517e..488b231 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -55,7 +55,7 @@
 		/* MRC cache found */
 		pei_data->saved_data_size = cache->size;
 		pei_data->saved_data = &cache->data[0];
-	} else if (pei_data->boot_mode == SLEEP_STATE_S3) {
+	} else if (pei_data->boot_mode == ACPI_S3) {
 		/* Waking from S3 and no cache. */
 		printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
 		post_code(POST_RESUME_FAILURE);
@@ -63,7 +63,7 @@
 	} else {
 		printk(BIOS_DEBUG, "No MRC cache found.\n");
 #if CONFIG_EC_GOOGLE_CHROMEEC
-		if (pei_data->boot_mode == SLEEP_STATE_S0) {
+		if (pei_data->boot_mode == ACPI_S0) {
 			/* Ensure EC is running RO firmware. */
 			google_chromeec_check_ec_image(EC_IMAGE_RO);
 		}
@@ -104,7 +104,7 @@
 	/* Basic memory sanity test */
 	quick_ram_check();
 
-	if (pei_data->boot_mode != SLEEP_STATE_S3) {
+	if (pei_data->boot_mode != ACPI_S3) {
 		cbmem_initialize_empty();
 	} else if (cbmem_initialize()) {
 #if CONFIG_HAVE_ACPI_RESUME

src/soc/intel/broadwell/romstage/romstage.c

diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index c6ffe7a..f2b28a5 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -98,7 +98,7 @@
 	params->pei_data->boot_mode = params->power_state->prev_sleep_state;
 
 #if CONFIG_ELOG_BOOT_COUNT
-	if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
+	if (params->power_state->prev_sleep_state != ACPI_S3)
 		boot_count_increment();
 #endif
 
@@ -117,12 +117,12 @@
 	handoff = romstage_handoff_find_or_add();
 	if (handoff != NULL)
 		handoff->s3_resume = (params->power_state->prev_sleep_state ==
-				      SLEEP_STATE_S3);
+				      ACPI_S3);
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
 #if CONFIG_LPC_TPM
-	init_tpm(params->power_state->prev_sleep_state == SLEEP_STATE_S3);
+	init_tpm(params->power_state->prev_sleep_state == ACPI_S3);
 #endif
 }