diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index 4722dfe..0a65165 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -746,19 +746,19 @@
  * DDR3 uses flyby topology where the clock signal takes a different path
  * than the data signal, to allow for better signal intergrity.
  * Therefore the delay on the data signals needs to account for this.
- * This is done by sampleling the DQS write (tx) signal back over
- * the DQ signal and looking for delay values where the sample transitions
+ * This is done by sampling the DQS write (tx) signal back over the DQ
+ * signal and looking for delay values where the sample transitions
  * from high to low.
  * Here the following is done:
- * - enable write levelling on the first populated rank
- * - disable output on other populated ranks
- * - start from safe DQS (tx) delays (other transitions can be
- *   found at different starting values but are generally bad)
+ * - Enable write levelling on the first populated rank.
+ * - Disable output on other populated ranks.
+ * - Start from safe DQS (tx) delays. Other transitions can be
+ *   found at different starting values but are generally bad.
  * - loop0: decrease DQS (tx) delays until low is sampled,
  *   loop1: increase DQS (tx) delays until high is sampled,
- *   That way we are sure to hit a low-high transition
- * - put all ranks in normal mode of operation again
- * - note: All ranks need to be leveled together
+ *   This way, we are sure to have hit a low-high transition.
+ * - Put all ranks in normal mode of operation again.
+ * Note: All ranks need to be leveled together.
  */
 void search_write_leveling(struct sysinfo *s)
 {