soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS
a) Add LTR disqualification in D3 to ensure PMC ignores LTR
from UFS IP as it is infinite.
b) Remove LTR disqualification in _PS0 to ensure PMC stops
ignoring LTR from UFS IP during D3 exit.
c) Add Kconfig (SOC_INTEL_UFS_LTR_DISQUALIFY) check to apply
this LTR WA.
BUG=b:252975357
TEST=build and boot nirwen and see no issues in PLT runs
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index fe7b3a2..548ef3d 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -428,6 +428,7 @@
config ALDERLAKE_ENABLE_SOC_WORKAROUND
bool
default y
+ select SOC_INTEL_UFS_LTR_DISQUALIFY
select SOC_INTEL_UFS_OCP_TIMER_DISABLE
help
Selects the workarounds applicable for Alder Lake SoC.
diff --git a/src/soc/intel/alderlake/include/soc/ufs.h b/src/soc/intel/alderlake/include/soc/ufs.h
index 3b5e33d..e3a98f2 100644
--- a/src/soc/intel/alderlake/include/soc/ufs.h
+++ b/src/soc/intel/alderlake/include/soc/ufs.h
@@ -22,6 +22,7 @@
#define R_SCS_PCR_5820 0x5820
#define R_SCS_PCR_5C20 0x5C20
#define R_SCS_PCR_1078 0x1078
-#define R_PMC_PWRM_LTR_IGN 0x1B0C
+#define R_PMC_PWRM_LTR_IGN 0x1b0c
+#define PCH_PWRM_BASE_SIZE 0x1e30
#endif
diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig
index 2b102bc..bf5fa56 100644
--- a/src/soc/intel/common/block/acpi/Kconfig
+++ b/src/soc/intel/common/block/acpi/Kconfig
@@ -56,4 +56,9 @@
work around the Silicon Issue due to which LTR mechanism
doesn't work.
+config SOC_INTEL_UFS_LTR_DISQUALIFY
+ bool
+ help
+ LTR needs to be disqualified for UFS in D3 to ensure PMC
+ ignores LTR from UFS IP which is infinite.
endif
diff --git a/src/soc/intel/common/block/acpi/acpi/ufs.asl b/src/soc/intel/common/block/acpi/acpi/ufs.asl
index f7cb9f3..a2ddaa9 100644
--- a/src/soc/intel/common/block/acpi/acpi/ufs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/ufs.asl
@@ -1,7 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <soc/iomap.h>
#include <soc/pcr_ids.h>
#include <soc/ufs.h>
+#define TRUE 1
+#define FALSE 0
+
Scope (\_SB.PCI0)
{
Device (UFS)
@@ -59,6 +63,18 @@
PGEN, 1
}
+ OperationRegion(PWMR, SystemMemory, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE)
+ Field(PWMR, DWordAcc, NoLock, Preserve)
+ {
+ Offset(R_PMC_PWRM_LTR_IGN),
+ , 18,
+ LTRU, 1, /* Bit 18 - Ignore LTR from UFS X2 */
+ }
+
+ Method (ULTR, 1, Serialized) {
+ LTRU = Arg0
+ }
+
Method (_PS0, 0, Serialized)
{
/* Disable PG */
@@ -67,6 +83,11 @@
/* Set BIT[1:0] = 00b - Power State D0 */
PSTA &= 0xFFFFFFFC
+#if CONFIG(SOC_INTEL_UFS_LTR_DISQUALIFY)
+ /* Remove Disqualification of LTR from UFS IP */
+ ULTR (FALSE)
+#endif
+
#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE)
/* Disable OCP Timer in SCS UFS IOSF Bridge */
OCPD ()
@@ -75,6 +96,11 @@
Method (_PS3, 0, Serialized)
{
+#if CONFIG(SOC_INTEL_UFS_LTR_DISQUALIFY)
+ /* Disqualify LTR from UFS IP */
+ ULTR (TRUE)
+#endif
+
/* Enable PG */
PGEN = 1
}