soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S
Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 0357ba9..86366bf 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -105,11 +105,7 @@
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
- select SOC_INTEL_COMMON_BLOCK_TCSS
select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
- select SOC_INTEL_COMMON_BLOCK_USB4
- select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
- select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BASECODE
@@ -126,6 +122,15 @@
select UDELAY_TSC
select UDK_202005_BINDING
+config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT
+ bool
+ default y if !SOC_INTEL_ALDERLAKE_PCH_S
+ default n if SOC_INTEL_ALDERLAKE_PCH_S
+ select SOC_INTEL_COMMON_BLOCK_TCSS
+ select SOC_INTEL_COMMON_BLOCK_USB4
+ select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
+ select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
+
config ALDERLAKE_CONFIGURE_DESCRIPTOR
bool
help
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index a03c42a..24c348a 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -40,7 +40,7 @@
ramstage-y += pcie_rp.c
ramstage-y += pmc.c
ramstage-y += reset.c
-ramstage-y += retimer.c
+ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT) += retimer.c
ramstage-y += soundwire.c
ramstage-y += systemagent.c
ramstage-y += tcss.c