nb/intel/sandybridge: Add ACPI DMAR table
Add a DMAR table to advertise IOMMU and IRQ remapping capabilities to
the OS.
Tested with kontron/ktqm77. Under Linux, the table is detected and
interrupt remapping is enabled automatically.
Change-Id: Id6ee601a0a8543ed09c6bb8d308a3a3549fc34e5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12195
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index dc1d668..eebf99c 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -28,6 +28,7 @@
#include "sandybridge.h"
#include <cbmem.h>
#include <drivers/intel/gma/intel_bios.h>
+#include <southbridge/intel/bd82x6x/pch.h>
unsigned long acpi_fill_mcfg(unsigned long current)
{
@@ -207,3 +208,52 @@
init_igd_opregion(opregion);
return opregion;
}
+
+static unsigned long acpi_fill_dmar(unsigned long current)
+{
+ const struct device *const igfx = dev_find_slot(0, PCI_DEVFN(2, 0));
+
+ if (igfx && igfx->enabled) {
+ const unsigned long tmp = current;
+ current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1);
+ current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0);
+ current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 1);
+ acpi_dmar_drhd_fixup(tmp, current);
+ }
+
+ const unsigned long tmp = current;
+ current += acpi_create_dmar_drhd(current,
+ DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE2);
+ current += acpi_create_dmar_drhd_ds_ioapic(current,
+ 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
+ size_t i;
+ for (i = 0; i < 8; ++i)
+ current += acpi_create_dmar_drhd_ds_msi_hpet(current,
+ 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, i);
+ acpi_dmar_drhd_fixup(tmp, current);
+
+ return current;
+}
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long northbridge_write_acpi_tables(struct device *const dev,
+ unsigned long current,
+ struct acpi_rsdp *const rsdp)
+{
+ const u32 capid0_a = pci_read_config32(dev, 0xe4);
+ if (capid0_a & (1 << 23))
+ return current;
+
+ printk(BIOS_DEBUG, "ACPI: * DMAR\n");
+ acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
+ acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
+ current += dmar->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, dmar);
+
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+
+ return current;
+}
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index c718353..08a0c9d 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -268,6 +268,7 @@
.init = NULL,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
+ .write_acpi_tables = northbridge_write_acpi_tables,
};
static void mc_read_resources(device_t dev)
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 853dd1c..0a1f20a 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -62,6 +62,8 @@
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__
+#include <rules.h>
+
/* Device 0:0.0 PCI configuration space (Host Bridge) */
#define EPBAR 0x40
@@ -215,6 +217,13 @@
void report_platform_info(void);
#endif /* !__SMM__ */
+#if ENV_RAMSTAGE
+#include <device/device.h>
+
+struct acpi_rsdp;
+unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp);
+#endif
+
#define MRC_DATA_ALIGN 0x1000
#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))