tree ceec2da08c2c5fd860e84e4c75587021c6655e0b
parent a1a3be1df84fd76c9195dff182e77fe391101c7f
author Werner Zeh <werner.zeh@siemens.com> 1671701035 +0100
committer Martin L Roth <gaumless@gmail.com> 1671811010 +0000

mb/siemens/mc_apl{4,7}: Limit I2C bus speed to 100 kHz on bus 7

Due to a high I2C bus load on the mainboard I2C frequency of 400 kHz
leads to poor signaling. Therefore limit the I2C speed to 100 kHz for
this bus. In addition, add a generic I2C device with 100 kHz bus speed
to the devicetree so that the OS will not switch to higher clock rates,
too.

Test= Measure the I2C signals at coreboot and OS runtime and ensure the
clock is always at 100 kHz.

Change-Id: I6b0a642cd3f5b77331663ac8c76ed0a116ae77ca
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71227
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>