nb/intel/x4x: Clean up raminit comments
Use C-style comments everywhere, and follow the coding style.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I3ef96c5f6553ad50cee7d7f5614128b62a89e4ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index 4362bd6..82dca44 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -278,7 +278,7 @@
s->dq_settings[channel][lane] = s->dqs_settings[channel][lane];
}
memset(dq_lower, 0, sizeof(dq_lower));
- /* Start from DQS settings */
+ /* Start from DQS settings */
memcpy(dq_setting, s->dqs_settings[channel], sizeof(dq_setting));
if (find_dq_limit(s, channel, dq_setting, dq_lower,
@@ -525,49 +525,49 @@
/* Is shifted by bits 2 later so u8 can be used to reduce size */
static const u8 emrs1_lut[8][4][4] = { /* [Config][Leveling Rank][Rank] */
- { /* Config 0: 2R2R */
+ { /* Config 0: 2R2R */
{0x11, 0x00, 0x91, 0x00},
{0x00, 0x11, 0x91, 0x00},
{0x91, 0x00, 0x11, 0x00},
{0x91, 0x00, 0x00, 0x11}
},
- { // Config 1: 2R1R
+ { /* Config 1: 2R1R */
{0x11, 0x00, 0x91, 0x00},
{0x00, 0x11, 0x91, 0x00},
{0x91, 0x00, 0x11, 0x00},
{0x00, 0x00, 0x00, 0x00}
},
- { // Config 2: 1R2R
+ { /* Config 2: 1R2R */
{0x11, 0x00, 0x91, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x91, 0x00, 0x11, 0x00},
{0x91, 0x00, 0x00, 0x11}
},
- { // Config 3: 1R1R
+ { /* Config 3: 1R1R */
{0x11, 0x00, 0x91, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x91, 0x00, 0x11, 0x00},
{0x00, 0x00, 0x00, 0x00}
},
- { // Config 4: 2R0R
+ { /* Config 4: 2R0R */
{0x11, 0x00, 0x00, 0x00},
{0x00, 0x11, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00}
},
- { // Config 5: 0R2R
+ { /* Config 5: 0R2R */
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x11, 0x00},
{0x00, 0x00, 0x00, 0x11}
},
- { // Config 6: 1R0R
+ { /* Config 6: 1R0R */
{0x11, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00}
},
- { // Config 7: 0R1R
+ { /* Config 7: 0R1R */
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x00, 0x00},
{0x00, 0x00, 0x11, 0x00},