soc/intel/common/pch: Add pch lockdown code
pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 466db09..e8023ba 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -21,6 +21,7 @@
#include <device/pci.h>
#include <fsp/util.h>
#include <intelblocks/xdci.h>
+#include <intelpch/lockdown.h>
#include <soc/acpi.h>
#include <soc/interrupt.h>
#include <soc/irq.h>
@@ -69,14 +70,6 @@
dev->ops = &cpu_bus_ops;
}
-static int get_lockdown_config(void)
-{
- const struct soc_intel_common_config *soc_config;
- soc_config = chip_get_common_soc_structure();
-
- return soc_config->chipset_lockdown;
-}
-
struct chip_operations soc_intel_skylake_ops = {
CHIP_NAME("Intel Skylake")
.enable_dev = &soc_enable,
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index ebfad66..00c7163 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -30,6 +30,7 @@
#include <fsp/api.h>
#include <fsp/util.h>
#include <intelblocks/xdci.h>
+#include <intelpch/lockdown.h>
#include <romstage_handoff.h>
#include <soc/acpi.h>
#include <soc/intel/common/vbt.h>
@@ -211,14 +212,6 @@
dev->ops = &cpu_bus_ops;
}
-static int get_lockdown_config(void)
-{
- const struct soc_intel_common_config *soc_config;
- soc_config = chip_get_common_soc_structure();
-
- return soc_config->chipset_lockdown;
-}
-
struct chip_operations soc_intel_skylake_ops = {
CHIP_NAME("Intel 6th Gen")
.enable_dev = &soc_enable,
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index fd1f5b2..e4818dc 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,24 +14,15 @@
*/
#include <arch/io.h>
-#include <bootstate.h>
-#include <chip.h>
#include <intelblocks/chip.h>
-#include <intelblocks/fast_spi.h>
#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
+#include <intelpch/lockdown.h>
#include <soc/pm.h>
-#include <string.h>
-#define PCR_DMI_GCS 0x274C
-#define PCR_DMI_GCS_BILD (1 << 0)
-
-static void lpc_lockdown_config(const struct soc_intel_common_config *config)
+static void lpc_lockdown_config(int chipset_lockdown)
{
/* Set Bios Interface Lock, Bios Lock */
- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
lpc_set_bios_interface_lock_down();
lpc_set_lock_enable();
}
@@ -49,60 +40,11 @@
write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
}
-static void dmi_lockdown_config(void)
+void soc_lockdown_config(int chipset_lockdown)
{
- /*
- * GCS reg of DMI
- *
- * When set, prevents GCS.BBS from being changed
- * GCS.BBS: (Boot BIOS Strap) This field determines the destination
- * of accesses to the BIOS memory range.
- * Bits Description
- * "0b": SPI
- * "1b": LPC/eSPI
- */
- pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
-}
-
-static void fast_spi_lockdown_config(const
- struct soc_intel_common_config *config)
-{
- /* Set FAST_SPI opcode menu */
- fast_spi_set_opcode_menu();
-
- /* Discrete Lock Flash PR registers */
- fast_spi_pr_dlock();
-
- /* Lock FAST_SPIBAR */
- fast_spi_lock_bar();
-
- /* Set Bios Interface Lock, Bios Lock */
- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
- /* Bios Interface Lock */
- fast_spi_set_bios_interface_lock_down();
-
- /* Bios Lock */
- fast_spi_set_lock_enable();
- }
-}
-
-static void platform_lockdown_config(void *unused)
-{
- const struct soc_intel_common_config *common_config;
- common_config = chip_get_common_soc_structure();
-
/* LPC lock down configuration */
- lpc_lockdown_config(common_config);
-
- /* SPI lock down configuration */
- fast_spi_lockdown_config(common_config);
-
- /* DMI lock down configuration */
- dmi_lockdown_config();
+ lpc_lockdown_config(chipset_lockdown);
/* PMC lock down configuration */
pmc_lockdown_config();
}
-
-BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,
- NULL);