coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at init

Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and
SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR
registers should be done with proper bitmask.

TEST=Compiles successfully and verified that the RES bits are preserved across
register writes.

Original-Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607
Original-Signed-off-by: Furquan Shaikh <>
Original-Tested-by: Furquan Shaikh <>
Original-Reviewed-by: Aaron Durbin <>
Original-Commit-Queue: Furquan Shaikh <>
(cherry picked from commit dfb196b4063e4f94d1ba9d5e2d19bae624ed46b3)
Signed-off-by: Marc Jones <>

Change-Id: I033a68b723fea83817aaa6402b86c78abd3e1da9
Reviewed-by: Paul Menzel <>
Reviewed-by: Aaron Durbin <>
Tested-by: build bot (Jenkins)
1 file changed