mb/intel/adlrvp: Remove ADLRVP_M mainboard
These boards are not commerically available so can be removed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Icc853a9df44a4a770db76e119644f0b4c7fcc2c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index 41beefa..1083ce2 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -64,23 +64,6 @@
select INTEL_LPSS_UART_FOR_CONSOLE
select SOC_INTEL_ALDERLAKE_PCH_P
-config BOARD_INTEL_ADLRVP_M
- select BOARD_INTEL_ADLRVP_COMMON
- select DRIVERS_UART_8250IO
- select MAINBOARD_USES_IFD_EC_REGION
- select SOC_INTEL_ALDERLAKE_PCH_M
-
-config BOARD_INTEL_ADLRVP_M_EXT_EC
- select BOARD_INTEL_ADLRVP_COMMON
- select DRIVERS_INTEL_PMC
- select FW_CONFIG
- select FW_CONFIG_SOURCE_CHROMEEC_CBI
- select INTEL_LPSS_UART_FOR_CONSOLE
- select MAINBOARD_HAS_TPM2
- select SOC_INTEL_ALDERLAKE_PCH_M
- select SPI_TPM
- select TPM_GOOGLE_CR50
-
config BOARD_INTEL_ADLRVP_N
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_UART_8250IO
@@ -125,15 +108,12 @@
default "adlrvp_rpl" if BOARD_INTEL_ADLRVP_RPL
default "adlrvp_rpl_ext_ec" if BOARD_INTEL_ADLRVP_RPL_EXT_EC
default "adlrvp_p_mchp" if BOARD_INTEL_ADLRVP_P_MCHP
- default "adlrvp_m" if BOARD_INTEL_ADLRVP_M
- default "adlrvp_m_ext_ec" if BOARD_INTEL_ADLRVP_M_EXT_EC
default "adlrvp_n" if BOARD_INTEL_ADLRVP_N
default "adlrvp_n_ext_ec" if BOARD_INTEL_ADLRVP_N_EXT_EC
config GBB_HWID
string
depends on CHROMEOS
- default "ADLRVPM TEST 4471" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
default "ADLRVPN TEST 7673" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
default "ADLRVPP TEST 2418"
@@ -149,7 +129,6 @@
default "Intel_adlrvp"
config DEVICETREE
- default "devicetree_m.cb" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
default "devicetree_n.cb" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
default "devicetree.cb"
@@ -161,8 +140,7 @@
choice
prompt "ON BOARD EC"
- default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_RPL
- default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC
+ default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC
help
This option allows you to select the on board EC to use.
Select whether the board has Intel EC or Chrome EC
@@ -184,21 +162,21 @@
select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC
select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC
- select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC
+ select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_N_EXT_EC
config UART_FOR_CONSOLE
int
default 0
config DRIVER_TPM_SPI_BUS
- default 0x2 if BOARD_INTEL_ADLRVP_RPL_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC
+ default 0x2 if BOARD_INTEL_ADLRVP_RPL_EXT_EC
config USE_PM_ACPI_TIMER
default n if BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_N
config TPM_TIS_ACPI_INTERRUPT
int
- default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3)
+ default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC # GPE0_DW2_3 (GPP_E3)
config GEN3_EXTERNAL_CLOCK_BUFFER
bool
diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name
index 2c89395..63e4ce1 100644
--- a/src/mainboard/intel/adlrvp/Kconfig.name
+++ b/src/mainboard/intel/adlrvp/Kconfig.name
@@ -9,12 +9,6 @@
config BOARD_INTEL_ADLRVP_P_MCHP
bool "Alderlake-P RVP with Microchip EC"
-config BOARD_INTEL_ADLRVP_M
- bool "Alderlake-M RVP"
-
-config BOARD_INTEL_ADLRVP_M_EXT_EC
- bool "Alderlake-M RVP with Chrome EC"
-
config BOARD_INTEL_ADLRVP_N
bool "Alderlake-N RVP"
diff --git a/src/mainboard/intel/adlrvp/Makefile.mk b/src/mainboard/intel/adlrvp/Makefile.mk
index d37abf5..b63953c 100644
--- a/src/mainboard/intel/adlrvp/Makefile.mk
+++ b/src/mainboard/intel/adlrvp/Makefile.mk
@@ -4,10 +4,7 @@
bootblock-y += bootblock.c
bootblock-$(CONFIG_CHROMEOS) += chromeos.c
-ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_M),y)
-bootblock-y += early_gpio_m.c
-ramstage-y += gpio_m.c
-else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
+ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
bootblock-y += early_gpio_n.c
ramstage-y += gpio_n.c
else
diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c
index bdbb079..4c2d1e5 100644
--- a/src/mainboard/intel/adlrvp/chromeos.c
+++ b/src/mainboard/intel/adlrvp/chromeos.c
@@ -14,8 +14,8 @@
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
};
- if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) ||
- CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
+ if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) ||
+ CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
else
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1);
@@ -40,8 +40,8 @@
return 0;
}
-#if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) ||\
- CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
+#if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) ||\
+ CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
int get_ec_is_trusted(void)
{
/* EC is trusted if not in RW. */
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index d761e87..9ac480d 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -39,7 +39,7 @@
/* Override dev tree settings per board */
}
-#if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
+#if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
{
struct smbios_type11 *t;
@@ -59,7 +59,7 @@
static void mainboard_enable(struct device *dev)
{
-#if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
+#if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
dev->ops->get_smbios_strings = mainboard_smbios_strings;
#endif
}
@@ -82,13 +82,9 @@
if (cpu_id == CPUID_RAPTORLAKE_J0)
return "vbt_adlrvp_rpl_lp5.bin";
return "vbt_adlrvp_lp5.bin";
- case ADL_M_LP5:
- return "vbt_adlrvp_m_lp5.bin";
case ADL_P_DDR5_1:
case ADL_P_DDR5_2:
return "vbt_adlrvp_ddr5.bin";
- case ADL_M_LP4:
- return "vbt_adlrvp_m_lp4.bin";
default:
return "vbt.bin";
}
diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c
index 7a6bb5d..3bdc230 100644
--- a/src/mainboard/intel/adlrvp/ramstage.c
+++ b/src/mainboard/intel/adlrvp/ramstage.c
@@ -81,8 +81,7 @@
static void variant_update_typec_init_config(void)
{
/* Skip filling aux bias gpio pads for Windows SKUs */
- if (!(CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC)
- || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC)))
+ if (!(CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC)))
return;
config_t *config = config_of_soc();
diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.mk b/src/mainboard/intel/adlrvp/spd/Makefile.mk
index 52ff89f..f503b6d 100644
--- a/src/mainboard/intel/adlrvp/spd/Makefile.mk
+++ b/src/mainboard/intel/adlrvp/spd/Makefile.mk
@@ -1,8 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only
SPD_SOURCES = adlrvp_lp4 # 0b000
-SPD_SOURCES += adlrvp_m_lp4 # 0b001
-SPD_SOURCES += adlrvp_m_lp5 # 0b002
+SPD_SOURCES += empty # 0b001
+SPD_SOURCES += empty # 0b002
SPD_SOURCES += adlrvp_lp5 # 0b003
SPD_SOURCES += empty # 0b004
SPD_SOURCES += empty # 0b005
diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp4.spd.hex
deleted file mode 100644
index 4960258..0000000
--- a/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp4.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 11 11 0E 16 29 B9 08 00 40 00 00 02 01 00 00
-48 00 04 FF 92 54 05 00 8C 00 90 A8 90 E0 0B F0
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp5.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp5.spd.hex
deleted file mode 100644
index df75f5b..0000000
--- a/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp5.spd.hex
+++ /dev/null
@@ -1,32 +0,0 @@
-23 10 13 0E 15 1A F9 08 00 40 00 00 0A 01 00 00
-48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0
-03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m/overridetree.cb
deleted file mode 100644
index cb9c3fc..0000000
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_m/overridetree.cb
+++ /dev/null
@@ -1,3 +0,0 @@
-chip soc/intel/alderlake
- device domain 0 on end
-end
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
deleted file mode 100644
index a3860c6..0000000
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
+++ /dev/null
@@ -1,34 +0,0 @@
-chip soc/intel/alderlake
- device domain 0 on
- device ref pch_espi on
- chip ec/google/chromeec
- use conn0 as mux_conn[0]
- use conn1 as mux_conn[1]
- device pnp 0c09.0 on end
- end
- end
- device ref pmc hidden
-
- # The pmc_mux chip driver is a placeholder for the
- # PMC.MUX device in the ACPI hierarchy.
- chip drivers/intel/pmc_mux
- device generic 0 on
- chip drivers/intel/pmc_mux/conn
- use usb2_port1 as usb2_port
- use tcss_usb3_port1 as usb3_port
- # SBU is fixed, HSL follows CC
- register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
- device generic 0 alias conn0 on end
- end
- chip drivers/intel/pmc_mux/conn
- use usb2_port2 as usb2_port
- use tcss_usb3_port2 as usb3_port
- # SBU is fixed, HSL follows CC
- register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
- device generic 1 alias conn1 on end
- end
- end
- end
- end
- end
-end