commit 9bb6646a5739daea5f74f0fd6c5b61768f06f833
author Felix Held <felix-coreboot@felixheld.de> Sat Mar 04 02:33:28 2023 +0100
committer Felix Held <felix-coreboot@felixheld.de> Wed Mar 08 12:00:36 2023 +0000
tree 5c034fa756b3e5409007bc2178feb93bdddcd599
parent c44c977e0936c9099ad78a6c8b24810db5c2d293

soc/amd/picasso/acpi: rework C state info table handling

Rework the way the C state info is generated before it gets passed to
acpigen_write_CST_package in generate_cpu_entries by separating the data
from the code. For this, the newly introduced common get_cstate_info
function is used. Separating the data from the code will eventually
allow moving generate_cpu_entries to the common AMD code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id6bd8879ce5968b24893b43041be98db55a4c3c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>

src/soc/amd/picasso/Kconfig

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 8d5bfa7..db2109b 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -30,6 +30,7 @@
 	select SOC_AMD_COMMON_BLOCK_ACPI
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_ACPI_ALIB
+	select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
 	select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
 	select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
 	select SOC_AMD_COMMON_BLOCK_AOAC

src/soc/amd/picasso/acpi.c

diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index c5a91d7..0bac92f 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -227,15 +227,33 @@
 	return pstate_count;
 }
 
+const acpi_cstate_t cstate_cfg_table[] = {
+	[0] = {
+		.ctype = 1,
+		.latency = 1,
+		.power = 0,
+	},
+	[1] = {
+		.ctype = 2,
+		.latency = 400,
+		.power = 0,
+	},
+};
+
+const acpi_cstate_t *get_cstate_config_data(size_t *size)
+{
+	*size = ARRAY_SIZE(cstate_cfg_table);
+	return cstate_cfg_table;
+}
+
 void generate_cpu_entries(const struct device *device)
 {
 	int logical_cores;
-	size_t pstate_count, cpu;
+	size_t cstate_count, pstate_count, cpu;
+	acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
 	struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
 	struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
 	uint32_t threads_per_core;
-	uint32_t cstate_base_address =
-		rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK;
 
 	const acpi_addr_t perf_ctrl = {
 		.space_id = ACPI_ADDRESS_SPACE_FIXED,
@@ -248,35 +266,8 @@
 		.addrl = PS_STS_REG,
 	};
 
-	const acpi_cstate_t cstate_info[] = {
-		[0] = {
-			.ctype = 1,
-			.latency = 1,
-			.power = 0,
-			.resource = {
-				.space_id = ACPI_ADDRESS_SPACE_FIXED,
-				.bit_width = 2,
-				.bit_offset = 2,
-				.addrl = 0,
-				.addrh = 0,
-			},
-		},
-		[1] = {
-			.ctype = 2,
-			.latency = 400,
-			.power = 0,
-			.resource = {
-				.space_id = ACPI_ADDRESS_SPACE_IO,
-				.bit_width = 8,
-				.bit_offset = 0,
-				.addrl = cstate_base_address + 1,
-				.addrh = 0,
-				.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS,
-			},
-		},
-	};
-
 	threads_per_core = get_threads_per_core();
+	cstate_count = get_cstate_info(cstate_values);
 	pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
 	logical_cores = get_cpu_count();
 
@@ -297,7 +288,7 @@
 
 		acpigen_write_PPC(0);
 
-		acpigen_write_CST_package(cstate_info, ARRAY_SIZE(cstate_info));
+		acpigen_write_CST_package(cstate_values, cstate_count);
 
 		acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
 					  CSD_HW_ALL, 0);