sb/intel/i82371eb: Add PIIX4 definitions
These new definitions will be used by two other changes.
Change-Id: I242244c444f36af188c871dce037a7a9250206cd
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38367
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 2b53010..a566af776 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -40,6 +40,11 @@
#define XBCS 0x4e /* X-Bus chip select register */
#define GENCFG 0xb0 /* General configuration register */
+#define GPO2223 (1<<28) /* GPO22/23 */
+#define RTCCFG 0xcb /* Real time clock configuration register */
+#define RTC_POS_DECODE (1<<5)
+#define UPPER_RAM_EN (1<<2)
+#define RTC_ENABLE (1<<0)
/* IDE */
#define IDETIM_PRI 0x40 /* IDE timing register, primary channel */