cpu/intel/socket_*: Clean up Kconfig files
Remove SSE when SSE is already selected by supported CPUs.
Add "config SOCKET_SPECIFIC_OPTIONS" section to socket_p/Kconfig.
Change-Id: If2265ac716e90720e7ccc550239737d40c2f7a0a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index 5b6ae7f..2ff419b 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -7,7 +7,6 @@
def_bool y
select CPU_INTEL_MODEL_106CX
select MMX
- select SSE
select SETUP_XIP_CACHE
config DCACHE_RAM_BASE
diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig
index 638653c..464a9b4 100644
--- a/src/cpu/intel/socket_BGA956/Kconfig
+++ b/src/cpu/intel/socket_BGA956/Kconfig
@@ -1,11 +1,13 @@
config CPU_INTEL_SOCKET_BGA956
bool
- select CPU_INTEL_MODEL_1067X
- select MMX
- select SSE
if CPU_INTEL_SOCKET_BGA956
+config SOCKET_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_INTEL_MODEL_1067X
+ select MMX
+
config DCACHE_RAM_BASE
hex
default 0xfefc0000
diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig
index 552ed70..e90b42a 100644
--- a/src/cpu/intel/socket_p/Kconfig
+++ b/src/cpu/intel/socket_p/Kconfig
@@ -1,11 +1,14 @@
config CPU_INTEL_SOCKET_P
bool
+
+if CPU_INTEL_SOCKET_P
+
+config SOCKET_SPECIFIC_OPTIONS
+ def_bool y
select CPU_INTEL_MODEL_1067X
select CPU_INTEL_MODEL_6FX
select MMX
-if CPU_INTEL_SOCKET_P
-
config DCACHE_RAM_BASE
hex
default 0xfefc0000