| commit | 9abc91cc451af09dc90505ae9be2d4f43f796373 | [log] [tgz] |
|---|---|---|
| author | Roger Wang <roger2.wang@lcfc.corp-partner.google.com> | Thu Jun 13 10:40:29 2024 +0800 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Tue Jun 18 21:52:54 2024 +0000 |
| tree | d80551afc266509b715e2e1b04b8a7fea8b31234 | |
| parent | 2b8367ed4b1a1a92a4f56dabab284aaceb53f6c7 [diff] |
mb/google/nissa/var/sundance: disable pcie port7 Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test. BUG=b:328147465 TEST=Build and check S0ix function and verify FAFT sleep funciton. Change-Id: I53f704ed11a5c63b5c079c6e60ce2fa32bbd8b1a Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb index 65d7e95..72cb317 100644 --- a/src/mainboard/google/brya/variants/sundance/overridetree.cb +++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb
@@ -273,6 +273,7 @@ device pci 00.0 on end end end + device ref pcie_rp7 off end device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0]