lynxpoint: Management Engine Updates
The ME9 requirements have added some registers and changed some
of the MBP state machine. Implement the changes found so far in
the ME9 BWG. There were a couple of reigster renames, but the
majority of th churn in the me.h header file is just introducing
the data structures in the same order as the ME9 BWG.
Change-Id: I51b0bb6620eff4979674ea99992ddab65a8abc18
Signed-Off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2620
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
index 5b266cc..1eb30a1 100644
--- a/src/southbridge/intel/lynxpoint/early_me.c
+++ b/src/southbridge/intel/lynxpoint/early_me.c
@@ -56,12 +56,12 @@
void intel_early_me_status(void)
{
struct me_hfs hfs;
- struct me_gmes gmes;
+ struct me_hfs2 hfs2;
pci_read_dword_ptr(&hfs, PCI_ME_HFS);
- pci_read_dword_ptr(&gmes, PCI_ME_GMES);
+ pci_read_dword_ptr(&hfs2, PCI_ME_HFS2);
- intel_me_status(&hfs, &gmes);
+ intel_me_status(&hfs, &hfs2);
}
int intel_early_me_init(void)
@@ -73,6 +73,7 @@
printk(BIOS_INFO, "Intel ME early init\n");
/* Wait for ME UMA SIZE VALID bit to be set */
+ /* FIXME: ME9 BGW indicates a 5 sec poll timeout. */
for (count = ME_RETRY; count > 0; --count) {
pci_read_dword_ptr(&uma, PCI_ME_UMA);
if (uma.valid)
@@ -147,6 +148,13 @@
pci_write_dword_ptr(&did, PCI_ME_H_GS);
+ /*
+ * The ME firmware does not respond with an ACK when NOMEM or ERROR
+ * are sent.
+ */
+ if (status == ME_INIT_STATUS_NOMEM || status == ME_INIT_STATUS_ERROR)
+ return 0;
+
/* Must wait for ME acknowledgement */
for (count = ME_RETRY; count > 0; --count) {
pci_read_dword_ptr(&hfs, PCI_ME_HFS);
@@ -195,7 +203,9 @@
/* Perform the requested reset */
if (reset) {
outb(reset, 0xcf9);
- hlt();
+ while (1) {
+ hlt();
+ }
}
return -1;
}