soc/intel/tigerlake: Disable MrcSafeConfig
This change disables MrcSafeConfig option during MRC training.
MrcSafeConfig was enabled as part of the early testing.
Now with FSP 2527, there is no need to set this config anymore.
BUG=b:150357377
BRANCH=master
TEST=build and boot ripto/volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40106
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c
index 7823cfe..8664547 100644
--- a/src/soc/intel/tigerlake/meminit.c
+++ b/src/soc/intel/tigerlake/meminit.c
@@ -239,7 +239,6 @@
/* LPDDR4x does not allow interleaved memory */
mem_cfg->DqPinsInterleaved = 0;
mem_cfg->ECT = board_cfg->ect;
- mem_cfg->MrcSafeConfig = 0x1;
read_md_spd(info, &spd_data, &spd_len);
mem_cfg->MemorySpdDataLen = spd_len;