| commit | 9a369718d668601da13030e9b57cd1a3e313cf5d | [log] [tgz] |
|---|---|---|
| author | Angel Pons <th3fanbus@gmail.com> | Fri Jul 03 20:36:50 2020 +0200 |
| committer | Angel Pons <th3fanbus@gmail.com> | Sun Jul 12 10:05:36 2020 +0000 |
| tree | c35f3283c38070998541b02a39910235c9617558 | |
| parent | d7bf3ad9397a367021e57d204438a178022aaa8c [diff] [blame] |
haswell: Factor out `max_ddr3_freq` All mainboards choose the maximum speed of DDR3-1600. Change-Id: I8863f9d1df950b924f596689ebf1bfda5d317e06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43120 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 7c27827..ca94813 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c
@@ -52,6 +52,7 @@ .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, .tseg_size = CONFIG_SMM_TSEG_SIZE, + .max_ddr3_freq = 1600, }; mainboard_fill_pei_data(&pei_data);