tree 5768782cf71c42f9c53cf41ffa12e7c93263a05d
parent ac2cb4262104ffb2dac229f061480df4a29d8064
author Felix Held <felix-coreboot@felixheld.de> 1621968308 +0200
committer Felix Held <felix-coreboot@felixheld.de> 1622129948 +0000

soc/amd/cezanne: add devicetree setting for PSPP policy

This allows boards to specify which PSPP policy (basically a dynamic
trade-off between power consumption and PCIe link speed) should be used
and also makes sure that the boards are using the expected PSPP policy
and not just the UPD default from the FSP binary that has already
changed once during the development.

BUG=b:188793754

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1b6459b2984711e72b79f5d4d90e04cb4b78d512
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54930
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>