tree 0aafc6898fff683ddf36c7f9565b1d56429cbbe7
parent ff8bf410d9596ac82b183cb62e2d8990c550ee4a
author Subrata Banik <subrata.banik@intel.com> 1471592856 +0530
committer Aaron Durbin <adurbin@chromium.org> 1476579085 +0200

soc/intel/skylake: Handle platform global reset

In FSP1.1 all the platform resets including global was handled
on its own without any intervention from coreboot.
In FSP2.0, any reset required will be notified to coreboot
and it is expected that coreboot will perform platform reset.

Hence, implement platform global reset hooks in coreboot. If Intel
ME is in non ERROR state then MEI message will able to perform
global reset else force global reset by writing 0x6 or 0xE to
0xCF9 port with PCH ETR3 register bit [20] set.

BUG=none
BRANCH=none
TEST=Verified platform global reset is working with MEI
message or writing to PCH ETR3.

Change-Id: I57e55caa6d20b15644bac686be8734d9652f21e5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16903
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>