smmrelocate: Remove dead TSEG code.
Change-Id: I786dd8295d310bfd21db49cfbe5ea39675b25b68
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10361
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index ec489ce..2283e7b 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -139,54 +139,11 @@
movl %ecx, %edx
shl $10, %edx
-#if CONFIG_SMM_TSEG
- movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */
- addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */
- andl $~1, %eax /* Remove lock bit */
-#else
movl $0xa0000, %eax
-#endif
subl %edx, %eax /* subtract offset, see above */
addr32 movl %eax, (%ebx)
-#if CONFIG_SMM_TSEG
- /* Check for SMRR capability in MTRRCAP[11] */
- movl $MTRRcap_MSR, %ecx
- rdmsr
- bt $11, %eax
- jnc skip_smrr
-
- /* TSEG base */
- movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */
- addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */
- andl $~1, %eax /* Remove lock bit */
- movl %eax, %ebx
-
- /* Set SMRR base address. */
- movl $SMRRphysBase_MSR, %ecx
- orl $MTRR_TYPE_WRBACK, %eax
- xorl %edx, %edx
- wrmsr
-
- /* Set SMRR mask. */
- movl $SMRRphysMask_MSR, %ecx
- movl $(~(CONFIG_SMM_TSEG_SIZE - 1) | MTRRphysMaskValid), %eax
- xorl %edx, %edx
- wrmsr
-
-#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
- /*
- * IED base is top 4M of TSEG
- */
- addl $(CONFIG_SMM_TSEG_SIZE - IED_SIZE), %ebx
- movl $(0x30000 + 0x8000 + 0x7eec), %eax
- addr32 movl %ebx, (%eax)
-#endif
-
-skip_smrr:
-#endif
-
/* The next section of code is potentially southbridge specific */
/* Clear SMI status */