mb/google/zoombini/variants/meowth: Make FPMCU interrupt level-triggered

Fix the IRQ configuration: it must be level-sensitive not edge-sensitive
(and match the GPIO configuration).

BUG=b:71986991
BRANCH=none
TEST=on Meowth, /proc/interrupts shows 'IO-APIC 46-fasteoi chromeos-ec'
then run 'ectool --name=cros_fp fpmode fingerup' and see the number of
interrupts incrementing and the MKBP event happening.

Change-Id: Iba8cff21d637fe6bf4ef5152fc01aaf98906477d
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/25110
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index e49cc5d..062c6ec 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -174,7 +174,7 @@
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
 				register "uid" = "1"
 				register "compat_string" = ""google,cros-ec-spi""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A22_IRQ)"
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A22_IRQ)"
 				device spi 0 on end
 			end
 		end # GSPI #1