mainboard/lenovo: Add ThinkCentre M710s (Skylake)
The processor may be a Pentium or 6/7th generation Core i3/i5/i7.
This port was tested on an i5-7400.
Working:
- Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads:
- SeaBIOS
- TianoCore EDK 2
- Internal flashing (from coreboot)
- PEG
- PCIe
- SATA
- M.2 SSD
- M.2 WLAN (+ Bluetooth)
- LAN
- USB
- Memory card reader
- CPU fan
- VGA (DP bridge)
- Display ports
- Audio (output)
- COM1
- TPM
Not Working:
- SuperIO related things
- Power button LED
- PCIe clock related things and AER issues (LiveCD)
- Some drm issue when using EDK 2 and libgfxinit (LiveCD)
- ME cleaner
Untested:
- Audio (input)
Won't Test:
- COM2 header
- LPT header
- PS/2 keyboard and mouse
Thanks to Nico Huber and everyone else on the IRC for helping me write
my first port!
Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80343
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig
new file mode 100644
index 0000000..799e689
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_LENOVO_THINKCENTRE_M710S
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_GMA_HAVE_VBT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_TPM2
+ select MEMORY_MAPPED_TPM
+ select SKYLAKE_SOC_PCH_H
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SOC_INTEL_KABYLAKE
+ select SUPERIO_ITE_IT8629E
+
+config MAINBOARD_DIR
+ default "lenovo/thinkcentre_m710s"
+
+config MAINBOARD_PART_NUMBER
+ default "ThinkCentre M710s"
+
+endif # BOARD_LENOVO_THINKCENTRE_M710S
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name
new file mode 100644
index 0000000..5a78582
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_LENOVO_THINKCENTRE_M710S
+ bool "ThinkCentre M710s"
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk b/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk
new file mode 100644
index 0000000..1df6980
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl b/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl
new file mode 100644
index 0000000..16990d4
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl b/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl
new file mode 100644
index 0000000..16990d4
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt b/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt
new file mode 100644
index 0000000..0c95cda
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/board_info.txt
@@ -0,0 +1,8 @@
+Category: desktop
+Board URL: https://psref.lenovo.com/syspool/Sys/PDF/ThinkCentre/ThinkCentre_M710_SFF/ThinkCentre_M710_SFF_Spec.pdf
+Board model: IB250MH
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2017
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c b/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c
new file mode 100644
index 0000000..061b544
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/bootblock.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8629e/it8629e.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8629E_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8629E_GPIO)
+
+void bootblock_mainboard_early_init(void)
+{
+ ite_reg_write(GPIO_DEV, 0x23, 0x49);
+ ite_reg_write(GPIO_DEV, 0x71, 0x09);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/data.vbt b/src/mainboard/lenovo/thinkcentre_m710s/data.vbt
new file mode 100644
index 0000000..4855687
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/data.vbt
Binary files differ
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
new file mode 100644
index 0000000..aa1f9b2
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
@@ -0,0 +1,194 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+ register "eist_enable" = "true"
+
+ device cpu_cluster 0 on end
+ device domain 0 on
+ device ref peg0 on # PCIE16X
+ # These configurations are technically for PCIe root
+ # ports. However, they are used as there is no
+ # equivalent for PEG devices.
+ register "PcieRpClkReqSupport[0]" = "true"
+ register "PcieRpClkReqNumber[0]" = "2"
+ register "PcieRpClkSrcNumber[0]" = "0"
+ end
+ device ref igpu on end
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC1), // USB30A
+ [1] = USB2_PORT_MID(OC1), // USB30B
+ [2] = USB2_PORT_MID(OC2), // F_USB30_1A
+ [3] = USB2_PORT_MID(OC2), // F_USB30_1B
+ [4] = USB2_PORT_MID(OC3), // F_USB30_2A
+ [5] = USB2_PORT_MID(OC3), // F_USB30_2B
+ [6] = USB2_PORT_MID(OC_SKIP), // M.2 Bluetooth
+ [7] = USB2_PORT_MID(OC5), // USB_LANA
+ [8] = USB2_PORT_MID(OC5), // USB_LANB
+ [9] = USB2_PORT_MID(OC_SKIP), // F_USB1 (Pins 5, 7)
+ [10] = USB2_PORT_MID(OC_SKIP), // F_USB1 (Pins 6, 8)
+ // Used by the SD/MMC reader.
+ [11] = USB2_PORT_MID(OC_SKIP), // F_USB2 (Pins 5, 7)
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC1), // USB30A
+ [1] = USB3_PORT_DEFAULT(OC1), // USB30B
+ [2] = USB3_PORT_DEFAULT(OC2), // F_USB30_1A
+ [3] = USB3_PORT_DEFAULT(OC2), // F_USB30_1B
+ [4] = USB3_PORT_DEFAULT(OC3), // F_USB30_2A
+ [5] = USB3_PORT_DEFAULT(OC3), // F_USB30_2B
+ }"
+ end
+ device ref thermal on end
+ device ref heci1 on end
+ device ref sata on
+ register "SataSalpSupport" = "true"
+ register "SataPortsEnable" = "{
+ [0] = true, // SATA1
+ [1] = true, // SATA2
+ [2] = true, // SATA3
+ }"
+ end
+ device ref pcie_rp5 on # USB_LAN
+ register "PcieRpEnable[4]" = "true"
+ register "PcieRpLtrEnable[4]" = "true"
+ register "PcieRpClkReqSupport[4]" = "true"
+ register "PcieRpClkReqNumber[4]" = "5"
+ register "PcieRpClkSrcNumber[4]" = "5"
+ register "PcieRpAdvancedErrorReporting[4]" = "true"
+ end
+ device ref pcie_rp7 on # PCIE1X_2
+ register "PcieRpEnable[6]" = "true"
+ register "PcieRpLtrEnable[6]" = "true"
+ register "PcieRpClkReqSupport[6]" = "true"
+ register "PcieRpClkReqNumber[6]" = "7"
+ register "PcieRpClkSrcNumber[6]" = "7"
+ register "PcieRpAdvancedErrorReporting[6]" = "true"
+ end
+ device ref pcie_rp8 on # PCIE1X_1
+ register "PcieRpEnable[7]" = "true"
+ register "PcieRpLtrEnable[7]" = "true"
+ register "PcieRpClkReqSupport[7]" = "true"
+ register "PcieRpClkReqNumber[7]" = "8"
+ register "PcieRpClkSrcNumber[7]" = "8"
+ register "PcieRpAdvancedErrorReporting[7]" = "true"
+ end
+ device ref pcie_rp11 on # M2_WIFI
+ register "PcieRpEnable[10]" = "true"
+ register "PcieRpLtrEnable[10]" = "true"
+ register "PcieRpClkReqSupport[10]" = "true"
+ register "PcieRpClkReqNumber[10]" = "1"
+ register "PcieRpClkSrcNumber[10]" = "1"
+ register "PcieRpAdvancedErrorReporting[10]" = "true"
+ end
+ device ref pcie_rp21 on # M2_SSD
+ register "PcieRpEnable[20]" = "true"
+ register "PcieRpLtrEnable[20]" = "true"
+ register "PcieRpClkReqSupport[20]" = "true"
+ register "PcieRpClkReqNumber[20]" = "6"
+ register "PcieRpClkSrcNumber[20]" = "2"
+ register "PcieRpAdvancedErrorReporting[20]" = "true"
+ end
+ device ref lpc_espi on
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ chip superio/ite/it8629e
+ register "TMPIN1.mode" = "THERMAL_DIODE" # THER_HD
+ register "TMPIN2.mode" = "THERMAL_MODE_DISABLED"
+ # Located close to VR MOSFET.
+ register "TMPIN3.mode" = "THERMAL_DIODE"
+
+ # CPU_FAN
+ register "FAN1" = "{
+ .mode = FAN_SMART_AUTOMATIC,
+ .smart = {
+ .tmpin = 3,
+ .tmp_off = 35,
+ .tmp_start = 60,
+ .tmp_full = 85,
+ .tmp_delta = 2,
+ .pwm_start = 20,
+ .slope = 24,
+ },
+ }"
+
+ register "FAN2.mode" = "FAN_MODE_OFF" # SYS_FAN
+ register "FAN3.mode" = "FAN_MODE_OFF" # AUX1_FAN
+ # TODO: Add support for 6 fans.
+ #register "FAN6.mode" = "FAN_MODE_OFF" # AUX2_FAN
+
+ register "ec.vin_mask" = "VIN_ALL"
+
+ # Vendor values dumped using util/superiotool.
+ device pnp 2e.0 off end
+ device pnp 2e.1 on # VGA_COM1A
+ io 0x60 = 0x03f8
+ irq 0x70 = 0x04
+ irq 0xf1 = 0x50
+ end
+ device pnp 2e.2 off end
+ device pnp 2e.3 off end
+ device pnp 2e.4 on
+ io 0x60 = 0x0a30
+ io 0x62 = 0x0230
+ irq 0x70 = 0x09
+ irq 0xf0 = 0x40
+ end
+ device pnp 2e.5 on # KB_MS (PS/2 Keyboard)
+ io 0x60 = 0x0060
+ io 0x62 = 0x0064
+ irq 0x70 = 0x01
+ irq 0x71 = 0x02
+ irq 0xf0 = 0x48
+ end
+ device pnp 2e.6 on # KB_MS (PS/2 Mouse)
+ irq 0x70 = 0x0c
+ irq 0x71 = 0x02
+ end
+ device pnp 2e.7 on
+ irq 0x25 = 0x11
+ irq 0x26 = 0x04
+ irq 0x28 = 0x81
+ irq 0x2a = 0x0d
+ irq 0x2c = 0x01
+ io 0x60 = 0x0000
+ io 0x62 = 0x0a00
+ io 0x64 = 0x0000
+ irq 0x70 = 0x00
+ irq 0x71 = 0x09
+ irq 0x72 = 0x20
+ irq 0x73 = 0x38
+ irq 0xb8 = 0x11
+ irq 0xbc = 0xc0
+ irq 0xbd = 0x03
+ irq 0xc0 = 0x01
+ irq 0xc1 = 0x04
+ irq 0xc3 = 0x41
+ irq 0xc8 = 0x01
+ irq 0xc9 = 0x04
+ irq 0xcb = 0x01
+ irq 0xe9 = 0x07
+ irq 0xf0 = 0x10
+ irq 0xf4 = 0x0c
+ irq 0xf6 = 0x0e
+ irq 0xf8 = 0x08
+ irq 0xf9 = 0x02
+ irq 0xfc = 0x7c
+ end
+ device pnp 2e.8 on
+ io 0x60 = 0x0270
+ irq 0x70 = 0x08
+ end
+ device pnp 2e.a off end
+ end
+ chip drivers/pc80/tpm
+ device pnp c31.0 on end
+ end
+ end
+ device ref pmc on end
+ device ref hda on end
+ device ref smbus on end
+ device ref gbe on end # USB_LAN (maps to PCIe RP5)
+ end
+end
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl b/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl
new file mode 100644
index 0000000..184fee0
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725
+)
+{
+ #include <acpi/dsdt_top.asl>
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <soc/intel/common/block/acpi/acpi/platform.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+ Device (\_SB.PCI0) {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads b/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads
new file mode 100644
index 0000000..e562443
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/gpio.h b/src/mainboard/lenovo/thinkcentre_m710s/gpio.h
new file mode 100644
index 0000000..fcb1b91
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/gpio.h
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+static const struct pad_config gpio_table[] = {
+
+ /* ------- GPIO Community 0 ------- */
+
+ /* ------- GPIO Group GPP_A ------- */
+
+ PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), // KBRST#
+ PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), // LPC_AD0
+ PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), // LPC_AD1
+ PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), // LPC_AD2
+ PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), // LPC_AD3
+ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), // LPC_FRAME#
+ PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), // LPC_SERIRQ
+ PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1), // LPC_DRQ#0
+ PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), // TPM_CLKRUN
+ PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), // CLK_LPC_24M
+ PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), // CLK_PCI_24M
+ PAD_CFG_NF(GPP_A11, NONE, PLTRST, NF1), // SIO_PME#
+ PAD_CFG_GPO(GPP_A12, 1, PLTRST), // BMBUSY#
+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // PCH_SUSWARN#
+ PAD_NC(GPP_A14, NONE),
+ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // PCH_SUSACK#
+ PAD_NC(GPP_A16, NONE),
+ PAD_NC(GPP_A17, NONE),
+ PAD_NC(GPP_A18, NONE),
+ PAD_NC(GPP_A19, NONE),
+ PAD_CFG_GPO(GPP_A20, 1, PLTRST), // TPM_GPIO
+ PAD_NC(GPP_A21, NONE),
+ PAD_NC(GPP_A22, NONE),
+ PAD_CFG_GPO(GPP_A23, 1, PLTRST), // TPM_EN
+
+ /* ------- GPIO Group GPP_B ------- */
+
+ PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI), // FUSB_G1
+ PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, PLTRST, OFF, ACPI), // FUSB_G2
+ PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, PLTRST, OFF, ACPI), // VR_ALERT#
+ PAD_NC(GPP_B3, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, PLTRST, OFF, ACPI), // LPT_DET#
+ PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI), // COM_GPIO1
+ PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI), // CLKREQ_WLAN#
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // PCIEX16_PRSNT
+ PAD_NC(GPP_B8, NONE), // PCI_PRSNT#
+ PAD_NC(GPP_B9, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI), // CLKREQ_LAN#
+ PAD_NC(GPP_B11, NONE),
+ PAD_CFG_GPO(GPP_B12, 1, DEEP), // SLP_S0#
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST#
+ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), // SPKR
+ PAD_NC(GPP_B15, NONE),
+ PAD_NC(GPP_B16, NONE),
+ PAD_NC(GPP_B17, NONE),
+ PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1), // LPSS_GSPI0_MOSI
+ PAD_NC(GPP_B19, NONE),
+ PAD_CFG_GPI_SMI(GPP_B20, NONE, DEEP, EDGE_SINGLE, INVERT), // SMI#
+ PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, PLTRST, OFF, ACPI), // OE#
+ PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1), // LPSS_GSPI1_MOSI
+ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), // EXI_STRAP
+
+ /* ------- GPIO Community 1 ------- */
+
+ /* ------- GPIO Group GPP_C ------- */
+
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMBCLK
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMBDATA
+ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), // TLS_STRAP
+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+ PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), // ESPI_LPC_STRAP
+ /* GPP_C6 - RESERVED */ // SML1_CLK
+ /* GPP_C7 - RESERVED */ // SML1_DATA
+ PAD_NC(GPP_C8, NONE),
+ PAD_NC(GPP_C9, NONE),
+ PAD_NC(GPP_C10, NONE),
+ PAD_NC(GPP_C11, NONE),
+ PAD_CFG_GPO(GPP_C12, 1, PLTRST), // TPM_DISABLE
+ PAD_CFG_GPO(GPP_C13, 0, PLTRST), // SSD_SATA_DEVSLP
+ PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, PLTRST, OFF, ACPI), // TPM_PRESENT#
+ PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, PLTRST, OFF, ACPI), // M2_SSD_DET#
+ PAD_NC(GPP_C16, NONE),
+ PAD_NC(GPP_C17, NONE),
+ PAD_NC(GPP_C18, NONE),
+ PAD_NC(GPP_C19, NONE),
+ PAD_NC(GPP_C20, NONE),
+ PAD_NC(GPP_C21, NONE), // UART2_TXD
+ PAD_NC(GPP_C22, NONE),
+ PAD_NC(GPP_C23, NONE),
+
+ /* ------- GPIO Group GPP_D ------- */
+
+ PAD_NC(GPP_D0, NONE),
+ PAD_NC(GPP_D1, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI), // PD_PCH_GPP_D_2
+ PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), // PD_PCH_GPP_D_3
+ PAD_NC(GPP_D4, NONE),
+ PAD_NC(GPP_D5, NONE),
+ PAD_NC(GPP_D6, NONE),
+ PAD_NC(GPP_D7, NONE),
+ PAD_NC(GPP_D8, NONE),
+ PAD_NC(GPP_D9, NONE),
+ PAD_NC(GPP_D10, NONE),
+ PAD_NC(GPP_D11, NONE),
+ PAD_NC(GPP_D12, NONE),
+ PAD_NC(GPP_D13, NONE),
+ PAD_CFG_GPO(GPP_D14, 0, PLTRST), // GPP_D14
+ PAD_NC(GPP_D15, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI), // GPP_D16
+ PAD_NC(GPP_D17, NONE),
+ PAD_NC(GPP_D18, NONE),
+ PAD_NC(GPP_D19, NONE),
+ PAD_NC(GPP_D20, NONE),
+ PAD_NC(GPP_D21, NONE),
+ PAD_NC(GPP_D22, NONE),
+ PAD_NC(GPP_D23, NONE),
+
+ /* ------- GPIO Group GPP_E ------- */
+
+ PAD_NC(GPP_E0, NONE),
+ PAD_NC(GPP_E1, NONE),
+ PAD_NC(GPP_E2, NONE),
+ PAD_NC(GPP_E3, NONE),
+ PAD_NC(GPP_E4, NONE),
+ PAD_NC(GPP_E5, NONE),
+ PAD_NC(GPP_E6, NONE),
+ PAD_NC(GPP_E7, NONE),
+ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), // SATA_LED#
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC1#
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), // USB_OC2#
+ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), // USB_OC3#
+ PAD_CFG_GPO(GPP_E12, 1, DEEP), // VISACH2_D3
+
+ /* ------- GPIO Group GPP_F ------- */
+
+ PAD_NC(GPP_F0, NONE),
+ PAD_NC(GPP_F1, NONE),
+ PAD_NC(GPP_F2, NONE),
+ PAD_NC(GPP_F3, NONE),
+ PAD_NC(GPP_F4, NONE),
+ PAD_NC(GPP_F5, NONE),
+ PAD_NC(GPP_F6, NONE),
+ PAD_NC(GPP_F7, NONE),
+ PAD_NC(GPP_F8, NONE),
+ PAD_NC(GPP_F9, NONE),
+ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), // PCH_CONFIG_JUMPER
+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI), // PCH_RSVD
+ PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST), // SV_ADVANCE_GP48
+ PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), // GP39_GFX_CRB_DETECT
+ PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), // H_SKTOCC#
+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), // USB_OC4#
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), // USB_OC5#
+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), // USB_OC6#
+ PAD_CFG_NF(GPP_F18, NONE, PLTRST, NF1), // USB2_OCB7
+ PAD_NC(GPP_F19, NONE),
+ PAD_NC(GPP_F20, NONE),
+ PAD_NC(GPP_F21, NONE),
+ PAD_CFG_GPO(GPP_F22, 1, PLTRST), // PCH_GPIO_F22
+ PAD_NC(GPP_F23, NONE),
+
+ /* ------- GPIO Group GPP_G ------- */
+
+ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, PLTRST, OFF, ACPI), // BRD_ID0
+ PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, PLTRST, OFF, ACPI), // BRD_ID1
+ PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, PLTRST, OFF, ACPI), // BRD_ID2
+ PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI), // BRD_ID3
+ PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI), // BRD_ID4
+ PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, PLTRST, OFF, ACPI), // BRD_ID5
+ PAD_NC(GPP_G6, NONE),
+ PAD_NC(GPP_G7, NONE),
+ PAD_NC(GPP_G8, NONE),
+ PAD_NC(GPP_G9, NONE),
+ PAD_NC(GPP_G10, NONE),
+ PAD_NC(GPP_G11, NONE),
+ PAD_NC(GPP_G12, NONE),
+ PAD_NC(GPP_G13, NONE),
+ PAD_NC(GPP_G14, NONE),
+ PAD_NC(GPP_G15, NONE),
+ PAD_NC(GPP_G16, NONE),
+ PAD_NC(GPP_G17, NONE),
+ PAD_NC(GPP_G18, NONE),
+ PAD_NC(GPP_G19, NONE), // SMI#
+ PAD_CFG_GPO(GPP_G20, 1, PLTRST), // PCH_VGA_HOT_PLUG#
+ PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), // SPI_TPM_PIRQ
+ PAD_CFG_GPI_TRIG_OWN(GPP_G22, NONE, PLTRST, OFF, ACPI), // GPP_G22
+ PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, PLTRST, OFF, ACPI), // GPP_G23
+
+ /* ------- GPIO Group GPP_H ------- */
+
+ PAD_CFG_NF(GPP_H0, NONE, PLTRST, NF1), // CLKREQ_SSD#
+ PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), // PCIE1_PRSNT#
+ PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, PLTRST, OFF, ACPI), // PCIE2_PRSNT#
+ PAD_NC(GPP_H3, NONE),
+ PAD_CFG_GPO(GPP_H4, 1, PLTRST), // CHARGE_EN
+ PAD_NC(GPP_H5, NONE),
+ PAD_NC(GPP_H6, NONE),
+ PAD_NC(GPP_H7, NONE),
+ PAD_NC(GPP_H8, NONE),
+ PAD_NC(GPP_H9, NONE),
+ PAD_CFG_GPO(GPP_H10, 1, PLTRST), // WIRELESS_EN1
+ PAD_CFG_GPO(GPP_H11, 1, PLTRST), // WIRELESS_EN2
+ PAD_CFG_GPO(GPP_H12, 1, PLTRST), // GPP_H12
+ PAD_CFG_GPI_TRIG_OWN(GPP_H13, NONE, PLTRST, OFF, ACPI), // SEL#
+ PAD_NC(GPP_H14, NONE),
+ PAD_NC(GPP_H15, NONE),
+ PAD_NC(GPP_H16, NONE),
+ PAD_NC(GPP_H17, NONE),
+ PAD_NC(GPP_H18, NONE),
+ PAD_NC(GPP_H19, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, PLTRST, OFF, ACPI), // CHASSIS_ID1
+ PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, PLTRST, OFF, ACPI), // CHASSIS_ID2
+ PAD_NC(GPP_H22, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, DEEP, OFF, ACPI), // CLR_CMOS
+
+ /* ------- GPIO Community 2 ------- */
+
+ /* -------- GPIO Group GPD -------- */
+
+ PAD_CFG_NF(GPD0, NONE, PLTRST, NF1), // PCH_BATLOW#
+ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), // ACPRESENT
+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKE#
+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWRBTN#
+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SLP_S3#
+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SLP_S4#
+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+ PAD_CFG_GPO(GPD7, 1, PWROK), // ME_DIS
+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), // SLP_WLAN#
+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+ PAD_CFG_GPO(GPD11, 1, PWROK), // LAN_DISABLE#
+
+ /* ------- GPIO Community 3 ------- */
+
+ /* ------- GPIO Group GPP_I ------- */
+
+ PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), // VGA_HPD
+ PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), // DP1_HPD
+ PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), // DP2_HPD
+ PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), // GPP_I3
+ PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), // GPP_I4
+ PAD_CFG_GPO(GPP_I5, 1, PLTRST), // GPP_I5
+ PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), // GPP_I6
+ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), // DP1_DDC_SCL
+ PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), // DP1_DDC_SDA
+ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), // DP2_DDC_SCL
+ PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), // DP2_DDC_SDA
+};
+
+#endif /* CFG_GPIO_H */
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c b/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c
new file mode 100644
index 0000000..5983301
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0662, // Vendor/Device ID: Realtek ACL662
+ 0x17aa3102, // Subsystem ID
+ 12,
+ AZALIA_SUBVENDOR(0, 0x17aa3102),
+
+ AZALIA_PIN_CFG(0, 0x12, 0x40000000), // does not describe a jack or internal device
+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_REAR_PANEL,
+ AZALIA_LINE_OUT,
+ AZALIA_STEREO_MONO_1_8,
+ AZALIA_GREEN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC(
+ AZALIA_INTEGRATED,
+ AZALIA_INTERNAL,
+ AZALIA_SPEAKER,
+ AZALIA_OTHER_ANALOG,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_NO_JACK_PRESENCE_DETECT,
+ 2, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_REAR_PANEL,
+ AZALIA_MIC_IN,
+ AZALIA_STEREO_MONO_1_8,
+ AZALIA_PINK,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 3, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT,
+ AZALIA_MIC_IN,
+ AZALIA_STEREO_MONO_1_8,
+ AZALIA_BLACK,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 4, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_REAR_PANEL,
+ AZALIA_LINE_IN,
+ AZALIA_STEREO_MONO_1_8,
+ AZALIA_BLUE,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 3, 15
+ )),
+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT,
+ AZALIA_HP_OUT,
+ AZALIA_STEREO_MONO_1_8,
+ AZALIA_BLACK,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 15
+ )),
+ AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4047c62b), // does not describe a jack or internal device
+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+
+ 0x8086280b, // Vendor/Device ID: Intel HDMI
+ 0x80860101, // Subsystem ID
+ 4,
+ AZALIA_SUBVENDOR(2, 0x80860101),
+
+ AZALIA_PIN_CFG(2, 0x05, 0x58560010), // VGA Bridge
+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_DIGITAL_DISPLAY,
+ AZALIA_DIGITAL_OTHER_OUT,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 2, 0
+ )),
+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_DIGITAL_DISPLAY,
+ AZALIA_DIGITAL_OTHER_OUT,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 3, 0
+ )),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/ramstage.c b/src/mainboard/lenovo/thinkcentre_m710s/ramstage.c
new file mode 100644
index 0000000..d85da3b
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/ramstage.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+
+#include "gpio.h"
+
+static void init_mainboard(void *chip_info)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+struct chip_operations mainboard_ops = {
+ .init = init_mainboard,
+};
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/romstage.c b/src/mainboard/lenovo/thinkcentre_m710s/romstage.c
new file mode 100644
index 0000000..23f4cf4
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_m710s/romstage.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <string.h>
+
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <types.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG * const mem_cfg = &mupd->FspmConfig;
+
+ mem_cfg->DqPinsInterleaved = true;
+ mem_cfg->CaVrefConfig = 2;
+
+ struct spd_block blk = {
+ .addr_map = {0x50, 0x51, 0x52, 0x53},
+ };
+
+ get_spd_smbus(&blk);
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+ mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];
+ mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
+ dump_spd_info(&blk);
+
+ const u16 rcomp_resistors[] = {121, 75, 100};
+
+ assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors));
+ memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(rcomp_resistors));
+
+ const u16 rcomp_targets[] = {60, 26, 20, 20, 26};
+
+ assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets));
+ memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(rcomp_targets));
+}