tree 6548c22a05ac2ce7d682a020959c23347bf968ed
parent 33c0aac3b642b1f2a3cef5d3c32b150148eee90a
author Arthur Heymans <arthur@aheymans.xyz> 1607428178 +0100
committer Patrick Georgi <pgeorgi@google.com> 1612169105 +0000

drivers/intel/fsp2_0: Use coreboot postcar with FSP-T

Allow platforms to use the coreboot postcar code instead of calling
into FSP-M TempRamExit API.

There are several reasons to do this:
- Tearing down CAR is easy.
- Allows having control over MTRR's and caching in general.
- The MTRR's set up in postcar be it by coreboot or FSP-M are
  overwritten later on during CPU init so it does not matter.
- Avoids having to find a CBFS file before cbmem is up (this
  causes problems with cbfs_mcache)

Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>