cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.
This removes the need for a magic lapic in the devicetree.
Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index fd0a203..69c1469 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <cpu/intel/speedstep.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -473,3 +474,13 @@
.vendor = PCI_VID_INTEL,
.devices = pci_device_ids,
};
+
+bool southbridge_support_c5(void)
+{
+ return false;
+}
+
+bool southbridge_support_c6(void)
+{
+ return false;
+}