cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.
This removes the need for a magic lapic in the devicetree.
Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
index 0bfdbc9..7946e34 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -8,22 +8,13 @@
register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms
register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms
+ register "slfm" = "1"
+
device cpu_cluster 0 on
ops gm45_cpu_bus_ops
chip cpu/intel/socket_p
device lapic 0 on end
end
- chip cpu/intel/model_1067x
- # Magic APIC ID to locate this chip
- device lapic 0xACAC off end
-
- # Enable Super LFM
- register "slfm" = "1"
-
- # Enable C5, C6
- register "c5" = "1"
- register "c6" = "1"
- end
end
register "pci_mmio_size" = "2048"