tree 53af8c6c11a980690639e87e60cf5dc139a2baa0
parent 083702c32ed2e70fd49ec7b02a79731173970a6d
author Elyes HAOUAS <ehaouas@noos.fr> 1609853937 +0100
committer Arthur Heymans <arthur@aheymans.xyz> 1611220094 +0000

cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE

Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE".
It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets
should have at least 256K L2 cache. That is plenty for XIP RO cache of
bootblock + romstage and a 32K CAR.

Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>