commit 985821c4f2feda41ed2d1ab83f6ae7b8f15197bd
author Elyes HAOUAS <ehaouas@noos.fr> Tue Jan 05 14:38:57 2021 +0100
committer Arthur Heymans <arthur@aheymans.xyz> Thu Jan 21 09:08:14 2021 +0000
tree 53af8c6c11a980690639e87e60cf5dc139a2baa0
parent 083702c32ed2e70fd49ec7b02a79731173970a6d

cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE

Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE".
It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets
should have at least 256K L2 cache. That is plenty for XIP RO cache of
bootblock + romstage and a 32K CAR.

Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/cpu/intel/socket_LGA775/Kconfig

diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8db932c..537a0d1 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -17,7 +17,7 @@
 
 config DCACHE_RAM_SIZE
 	hex
-	default 0x4000 # 16 kB
+	default 0x8000 # 32 kB
 
 config DCACHE_BSP_STACK_SIZE
 	hex