soc/intel/cannonlake: Select common XHCI code

This patch select CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI to include
common xhci code block.

BUG=b:78109109
BRANCH=none
TEST=Build and boot cnlrvp

Change-Id: I7f1e59792159dae5835fbbe7fcb1604fc01893ba
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 92b0af0..a095fb9 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -72,6 +72,7 @@
 	select SOC_INTEL_COMMON_BLOCK_TIMER
 	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_BLOCK_XDCI
+	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_NHLT
 	select SOC_INTEL_COMMON_RESET
 	select SSE2
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index b64d804..fd9ce52 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
+#include <intelblocks/acpi.h>
 #include <intelblocks/xdci.h>
 #include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
@@ -28,7 +29,7 @@
 #include <string.h>
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-static const char *soc_acpi_name(const struct device *dev)
+const char *soc_acpi_name(const struct device *dev)
 {
 	if (dev->path.type == DEVICE_PATH_DOMAIN)
 		return "PCI0";
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index d764262..c38d19f 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -31,7 +31,9 @@
 	.init			= soc_xhci_init,
 	.ops_pci		= &pci_dev_ops_pci,
 	.scan_bus		= &scan_usb_bus,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 	.acpi_name		= &soc_acpi_name,
+#endif
 };
 
 static const unsigned short pci_device_ids[] = {